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From: "Matheus K. Ferst" <matheus.ferst@eldorado.org.br>
To: Richard Henderson <richard.henderson@linaro.org>,
	qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: lucas.castro@eldorado.org.br, luis.pires@eldorado.org.br,
	groug@kaod.org, david@gibson.dropbear.id.au
Subject: Re: [PATCH 07/33] target/ppc: Implement cntlzdm
Date: Tue, 26 Oct 2021 11:33:09 -0300	[thread overview]
Message-ID: <f6b312b9-7d07-c07b-de3e-1f8b72d37c50@eldorado.org.br> (raw)
In-Reply-To: <b46ddf0b-d8fa-ab15-4f6f-aa8a24ff7e45@linaro.org>

On 22/10/2021 20:16, Richard Henderson wrote:
> [E-MAIL EXTERNO] Não clique em links ou abra anexos, a menos que você 
> possa confirmar o remetente e saber que o conteúdo é seguro. Em caso de 
> e-mail suspeito entre imediatamente em contato com o DTI.
> 
> On 10/21/21 12:45 PM, matheus.ferst@eldorado.org.br wrote:
>> +uint64_t helper_CNTLZDM(uint64_t src, uint64_t mask)
>> +{
>> +    uint64_t sel_bit, count = 0;
>> +
>> +    while (mask != 0) {
>> +        sel_bit = 0x8000000000000000ULL >> clz64(mask);
>> +
>> +        if (src & sel_bit) {
>> +            break;
>> +        }
> 
> We need to count how many mask are set left of mask & src.
> How about
> 
>      sh = clz64(src & mask);
>      if (sh == 0) {
>          return 0;
>      }
>      return ctpop64(mask >> (64 - sh));
> 
> which could probably be implemented inline relatively easy.
> 

Thanks for this suggestion Richard, we'll try to inline it.

>> +static bool trans_CNTLZDM(DisasContext *ctx, arg_X *a)
>> +{
>> +    REQUIRE_64BIT(ctx);
>> +    REQUIRE_INSNS_FLAGS2(ctx, ISA310);
>> +#if defined(TARGET_PPC64)
>> +    gen_helper_CNTLZDM(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
>> +#else
>> +    qemu_build_not_reached();
>> +#endif
>> +    return true;
>> +}
> 
> Why the ifdef here?  Oh, I see. You could just use target_long in the 
> helper to avoid
> that.  And if not, you should move the helper into an ifdef too.
> 

That's the same case of cfuged. There is a vector version of this 
instruction (vclzdm) that is not 64-bits only (at least on paper), so it 
should receive i64 and cannot be inside an ifdef(TARGET_PPC64). I'll add 
this info to the commit message.

If we dismiss the possibility of a future 32-bits implementation of 
PowerISA v3.1, we can move the helper inside the ifdef and add 
REQUIRE_64BITS in vclzdm/vctzdm (and vcfuged, vpdepd, vpextd, etc.)

-- 
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>


  reply	other threads:[~2021-10-26 14:37 UTC|newest]

Thread overview: 84+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-21 19:45 [PATCH 00/33] PowerISA v3.1 instruction batch matheus.ferst
2021-10-21 19:45 ` [PATCH 01/33] target/ppc: introduce do_ea_calc matheus.ferst
2021-10-22 21:51   ` Richard Henderson
2021-10-22 21:57   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 02/33] target/ppc: move resolve_PLS_D to translate.c matheus.ferst
2021-10-22 22:01   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 03/33] target/ppc: Move load and store floating point instructions to decodetree matheus.ferst
2021-10-22 22:19   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 04/33] target/ppc: Implement PLFS, PLFD, PSTFS and PSTFD instructions matheus.ferst
2021-10-22 22:24   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 05/33] target/ppc: Move LQ and STQ to decodetree matheus.ferst
2021-10-22 22:53   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 06/33] target/ppc: Implement PLQ and PSTQ matheus.ferst
2021-10-22 22:54   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 07/33] target/ppc: Implement cntlzdm matheus.ferst
2021-10-22 23:16   ` Richard Henderson
2021-10-26 14:33     ` Matheus K. Ferst [this message]
2021-10-21 19:45 ` [PATCH 08/33] target/ppc: Implement cnttzdm matheus.ferst
2021-10-22 23:55   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 09/33] target/ppc: Implement pdepd instruction matheus.ferst
2021-10-23  0:04   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 10/33] target/ppc: Implement pextd instruction matheus.ferst
2021-10-23  0:26   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 11/33] target/ppc: Move vcfuged to vmx-impl.c.inc matheus.ferst
2021-10-23  0:31   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 12/33] target/ppc: Implement vclzdm/vctzdm instructions matheus.ferst
2021-10-23  0:34   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 13/33] target/ppc: Implement vpdepd/vpextd instruction matheus.ferst
2021-10-23  0:38   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 14/33] target/ppc: Implement vsldbi/vsrdbi instructions matheus.ferst
2021-10-23  4:07   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 15/33] target/ppc: Implement Vector Insert from GPR using GPR index insns matheus.ferst
2021-10-23  4:37   ` Richard Henderson
2021-10-23  4:40   ` Richard Henderson
2021-10-23 10:12     ` BALATON Zoltan
2021-10-23 18:36       ` Richard Henderson
2021-10-23 20:02         ` BALATON Zoltan
2021-10-23 20:09           ` Richard Henderson
2021-10-26 14:33     ` Matheus K. Ferst
2021-10-21 19:45 ` [PATCH 16/33] target/ppc: Implement Vector Insert Word from GPR using Immediate insns matheus.ferst
2021-10-23  4:42   ` Richard Henderson
2021-10-26 14:33     ` Matheus K. Ferst
2021-10-26 16:58       ` Richard Henderson
2021-10-26 18:45         ` Paul A. Clarke
2021-10-27 11:49           ` Matheus K. Ferst
2021-10-21 19:45 ` [PATCH 17/33] target/ppc: Implement Vector Insert from VSR using GPR index insns matheus.ferst
2021-10-23  4:48   ` Richard Henderson
2021-10-23  4:54   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 18/33] target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree matheus.ferst
2021-10-23  4:53   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 19/33] target/ppc: Implement Vector Extract Double to VSR using GPR index insns matheus.ferst
2021-10-23 20:01   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 20/33] target/ppc: Introduce REQUIRE_VSX macro matheus.ferst
2021-10-23 20:10   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 21/33] target/ppc: moved stxv and lxv from legacy to decodtree matheus.ferst
2021-10-23 20:34   ` Richard Henderson
2021-10-23 20:39     ` Richard Henderson
2021-10-23 20:46   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 22/33] target/ppc: moved stxvx and lxvx " matheus.ferst
2021-10-23 20:38   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 23/33] target/ppc: added the instructions LXVP and STXVP matheus.ferst
2021-10-23 20:48   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 24/33] target/ppc: added the instructions LXVPX and STXVPX matheus.ferst
2021-10-23 20:49   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 25/33] target/ppc: added the instructions PLXV and PSTXV matheus.ferst
2021-10-23 20:56   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 26/33] target/ppc: added the instructions PLXVP and PSTXVP matheus.ferst
2021-10-23 20:57   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 27/33] target/ppc: moved XXSPLTW to using decodetree matheus.ferst
2021-10-23 21:03   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 28/33] target/ppc: moved XXSPLTIB " matheus.ferst
2021-10-23 21:06   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 29/33] target/ppc: implemented XXSPLTI32DX matheus.ferst
2021-10-23 21:12   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 30/33] target/ppc: Implemented XXSPLTIW using decodetree matheus.ferst
2021-10-23 21:15   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 31/33] target/ppc: implemented XXSPLTIDP instruction matheus.ferst
2021-10-23 21:19   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 32/33] target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions matheus.ferst
2021-10-23 21:24   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 33/33] target/ppc: Implement lxvkq instruction matheus.ferst
2021-10-23 21:29   ` Richard Henderson
2021-10-22  2:06 ` [PATCH 00/33] PowerISA v3.1 instruction batch Richard Henderson
2021-10-22 11:13   ` Matheus K. Ferst

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