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* [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree
@ 2021-10-23 21:47 Philippe Mathieu-Daudé
  2021-10-23 21:47 ` [PATCH 01/33] tests/tcg: Fix some targets default cross compiler path Philippe Mathieu-Daudé
                   ` (33 more replies)
  0 siblings, 34 replies; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Hi,\r
\r
This series converts 2000+ lines of switch() code to decodetree\r
description, so this hard-to-review/modify switch is auto generated\r
by the decodetree script. This is a big win for maintenance (and\r
indeed the convertion revealed 2 bugs).\r
\r
Massive convertions are - beside being often boring - bug-prone.\r
In this series we re-start running the MSA tests (the tests are\r
run automagically in the 'build-user-static' job on gitlab CI).\r
\r
Although boring, the conversion is very clean, so I hope it will\r
be easy enough to review. The TRANS*() macros are heavily used.\r
\r
When possible, constant fields are hold with tcg_constant().\r
\r
Note, various opcodes can be optimized using TCG host vectors.\r
We won't address that in this series, as it makes the resulting\r
review harder. We will post that in a following series. Here we\r
simply dummy-convert.\r
\r
The resulting msa.decode file is quite pleasant to look at, and\r
the diff-stat is encouraging: number of LoC halved.\r
\r
Regards,\r
\r
Phil.\r
\r
git: https://gitlab.com/philmd/qemu.git tree/mips-msa-decodetree\r
Based-on: <20211023164329.328137-1-f4bug@amsat.org>\r
\r
Philippe Mathieu-Daudé (33):\r
  tests/tcg: Fix some targets default cross compiler path\r
  target/mips: Fix MSA MADDV.B opcode\r
  target/mips: Fix MSA MSUBV.B opcode\r
  tests/tcg/mips: Run MSA opcodes tests on user-mode emulation\r
  target/mips: Have check_msa_access() return a boolean\r
  target/mips: Use enum definitions from CPUMIPSMSADataFormat enum\r
  target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v\r
  target/mips: Convert MSA LDI opcode to decodetree\r
  target/mips: Introduce generic TRANS_CHECK() for decodetree helpers\r
  target/mips: Extract df_extract() helper\r
  target/mips: Convert MSA I5 instruction format to decodetree\r
  target/mips: Convert MSA BIT instruction format to decodetree\r
  target/mips: Convert MSA SHF opcode to decodetree\r
  target/mips: Convert MSA I8 instruction format to decodetree\r
  target/mips: Convert MSA load/store instruction format to decodetree\r
  target/mips: Convert MSA 2RF instruction format to decodetree\r
  target/mips: Convert MSA FILL opcode to decodetree\r
  target/mips: Convert MSA 2R instruction format to decodetree\r
  target/mips: Convert MSA VEC instruction format to decodetree\r
  target/mips: Convert MSA 3RF instruction format to decodetree\r
    (DF_HALF)\r
  target/mips: Convert MSA 3RF instruction format to decodetree\r
    (DF_WORD)\r
  target/mips: Convert MSA 3R instruction format to decodetree (part\r
    1/4)\r
  target/mips: Convert MSA 3R instruction format to decodetree (part\r
    2/4)\r
  target/mips: Convert MSA 3R instruction format to decodetree (part\r
    3/4)\r
  target/mips: Convert MSA 3R instruction format to decodetree (part\r
    4/4)\r
  target/mips: Convert MSA ELM instruction format to decodetree\r
  target/mips: Convert MSA COPY_U opcode to decodetree\r
  target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree\r
  target/mips: Convert MSA MOVE.V opcode to decodetree\r
  target/mips: Convert CFCMSA and CTCMSA opcodes to decodetree\r
  target/mips: Remove generic MSA opcode\r
  target/mips: Remove one MSA unnecessary decodetree overlap group\r
  target/mips: Adjust style in msa_translate_init()\r
\r
 tests/tcg/mips/ase-msa.mak         |   30 +\r
 target/mips/tcg/translate.h        |    9 +\r
 target/mips/tcg/msa.decode         |  231 ++-\r
 target/mips/tcg/msa_helper.c       |   64 +-\r
 target/mips/tcg/msa_translate.c    | 2781 +++++++---------------------\r
 MAINTAINERS                        |    1 +\r
 tests/tcg/configure.sh             |   14 +-\r
 tests/tcg/mips/Makefile.target     |    5 +\r
 tests/tcg/mips64/Makefile.target   |    9 +\r
 tests/tcg/mips64el/Makefile.target |   12 +\r
 tests/tcg/mipsel/Makefile.target   |    9 +\r
 11 files changed, 1052 insertions(+), 2113 deletions(-)\r
 create mode 100644 tests/tcg/mips/ase-msa.mak\r
 create mode 100644 tests/tcg/mips64/Makefile.target\r
 create mode 100644 tests/tcg/mips64el/Makefile.target\r
 create mode 100644 tests/tcg/mipsel/Makefile.target\r
\r
-- \r
2.31.1\r
\r


^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 01/33] tests/tcg: Fix some targets default cross compiler path
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-23 23:24   ` Richard Henderson
  2021-10-23 21:47 ` [PATCH 02/33] target/mips: Fix MSA MADDV.B opcode Philippe Mathieu-Daudé
                   ` (32 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

We do not want a shell command substitution, but a parameter
substitution (with assignment). Replace $() -> ${}, otherwise
the expanded command return an empty string and the $cross_cc
variable is not set.

Fixes: 634ef789f8e ("tests/tcg: add more default compilers to configure.sh")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 tests/tcg/configure.sh | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh
index 1f985ccfc0c..b8574165fa6 100755
--- a/tests/tcg/configure.sh
+++ b/tests/tcg/configure.sh
@@ -46,7 +46,7 @@ fi
 : ${cross_cc_aarch64="aarch64-linux-gnu-gcc"}
 : ${cross_cc_aarch64_be="$cross_cc_aarch64"}
 : ${cross_cc_cflags_aarch64_be="-mbig-endian"}
-: $(cross_cc_alpha="alpha-linux-gnu-gcc")
+: ${cross_cc_alpha="alpha-linux-gnu-gcc"}
 : ${cross_cc_arm="arm-linux-gnueabihf-gcc"}
 : ${cross_cc_cflags_armeb="-mbig-endian"}
 : ${cross_cc_hexagon="hexagon-unknown-linux-musl-clang"}
@@ -55,17 +55,17 @@ fi
 : ${cross_cc_i386="i686-linux-gnu-gcc"}
 : ${cross_cc_cflags_i386="-m32"}
 : ${cross_cc_m68k="m68k-linux-gnu-gcc"}
-: $(cross_cc_mips64el="mips64el-linux-gnuabi64-gcc")
-: $(cross_cc_mips64="mips64-linux-gnuabi64-gcc")
-: $(cross_cc_mipsel="mipsel-linux-gnu-gcc")
-: $(cross_cc_mips="mips-linux-gnu-gcc")
+: ${cross_cc_mips64el="mips64el-linux-gnuabi64-gcc"}
+: ${cross_cc_mips64="mips64-linux-gnuabi64-gcc"}
+: ${cross_cc_mipsel="mipsel-linux-gnu-gcc"}
+: ${cross_cc_mips="mips-linux-gnu-gcc"}
 : ${cross_cc_ppc="powerpc-linux-gnu-gcc"}
 : ${cross_cc_cflags_ppc="-m32"}
 : ${cross_cc_ppc64="powerpc64-linux-gnu-gcc"}
 : ${cross_cc_ppc64le="powerpc64le-linux-gnu-gcc"}
-: $(cross_cc_riscv64="riscv64-linux-gnu-gcc")
+: ${cross_cc_riscv64="riscv64-linux-gnu-gcc"}
 : ${cross_cc_s390x="s390x-linux-gnu-gcc"}
-: $(cross_cc_sh4="sh4-linux-gnu-gcc")
+: ${cross_cc_sh4="sh4-linux-gnu-gcc"}
 : ${cross_cc_cflags_sparc="-m32 -mv8plus -mcpu=ultrasparc"}
 : ${cross_cc_sparc64="sparc64-linux-gnu-gcc"}
 : ${cross_cc_cflags_sparc64="-m64 -mcpu=ultrasparc"}
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 02/33] target/mips: Fix MSA MADDV.B opcode
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
  2021-10-23 21:47 ` [PATCH 01/33] tests/tcg: Fix some targets default cross compiler path Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-23 21:47 ` [PATCH 03/33] target/mips: Fix MSA MSUBV.B opcode Philippe Mathieu-Daudé
                   ` (31 subsequent siblings)
  33 siblings, 0 replies; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

The result of the 'Vector Multiply and Add' opcode is incorrect
with Byte vectors. Probably due to a copy/paste error, commit
7a7a162adde mistakenly used the $wt (target register) instead
of $wd (destination register) as first operand. Fix that.

Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Fixes: 7a7a162adde ("target/mips: msa: Split helpers for MADDV.<B|H|W|D>")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa_helper.c | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
index e40c1b70575..d978909527f 100644
--- a/target/mips/tcg/msa_helper.c
+++ b/target/mips/tcg/msa_helper.c
@@ -3231,22 +3231,22 @@ void helper_msa_maddv_b(CPUMIPSState *env,
     wr_t *pws = &(env->active_fpu.fpr[ws].wr);
     wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
 
-    pwd->b[0]  = msa_maddv_df(DF_BYTE, pwt->b[0],  pws->b[0],  pwt->b[0]);
-    pwd->b[1]  = msa_maddv_df(DF_BYTE, pwt->b[1],  pws->b[1],  pwt->b[1]);
-    pwd->b[2]  = msa_maddv_df(DF_BYTE, pwt->b[2],  pws->b[2],  pwt->b[2]);
-    pwd->b[3]  = msa_maddv_df(DF_BYTE, pwt->b[3],  pws->b[3],  pwt->b[3]);
-    pwd->b[4]  = msa_maddv_df(DF_BYTE, pwt->b[4],  pws->b[4],  pwt->b[4]);
-    pwd->b[5]  = msa_maddv_df(DF_BYTE, pwt->b[5],  pws->b[5],  pwt->b[5]);
-    pwd->b[6]  = msa_maddv_df(DF_BYTE, pwt->b[6],  pws->b[6],  pwt->b[6]);
-    pwd->b[7]  = msa_maddv_df(DF_BYTE, pwt->b[7],  pws->b[7],  pwt->b[7]);
-    pwd->b[8]  = msa_maddv_df(DF_BYTE, pwt->b[8],  pws->b[8],  pwt->b[8]);
-    pwd->b[9]  = msa_maddv_df(DF_BYTE, pwt->b[9],  pws->b[9],  pwt->b[9]);
-    pwd->b[10] = msa_maddv_df(DF_BYTE, pwt->b[10], pws->b[10], pwt->b[10]);
-    pwd->b[11] = msa_maddv_df(DF_BYTE, pwt->b[11], pws->b[11], pwt->b[11]);
-    pwd->b[12] = msa_maddv_df(DF_BYTE, pwt->b[12], pws->b[12], pwt->b[12]);
-    pwd->b[13] = msa_maddv_df(DF_BYTE, pwt->b[13], pws->b[13], pwt->b[13]);
-    pwd->b[14] = msa_maddv_df(DF_BYTE, pwt->b[14], pws->b[14], pwt->b[14]);
-    pwd->b[15] = msa_maddv_df(DF_BYTE, pwt->b[15], pws->b[15], pwt->b[15]);
+    pwd->b[0]  = msa_maddv_df(DF_BYTE, pwd->b[0],  pws->b[0],  pwt->b[0]);
+    pwd->b[1]  = msa_maddv_df(DF_BYTE, pwd->b[1],  pws->b[1],  pwt->b[1]);
+    pwd->b[2]  = msa_maddv_df(DF_BYTE, pwd->b[2],  pws->b[2],  pwt->b[2]);
+    pwd->b[3]  = msa_maddv_df(DF_BYTE, pwd->b[3],  pws->b[3],  pwt->b[3]);
+    pwd->b[4]  = msa_maddv_df(DF_BYTE, pwd->b[4],  pws->b[4],  pwt->b[4]);
+    pwd->b[5]  = msa_maddv_df(DF_BYTE, pwd->b[5],  pws->b[5],  pwt->b[5]);
+    pwd->b[6]  = msa_maddv_df(DF_BYTE, pwd->b[6],  pws->b[6],  pwt->b[6]);
+    pwd->b[7]  = msa_maddv_df(DF_BYTE, pwd->b[7],  pws->b[7],  pwt->b[7]);
+    pwd->b[8]  = msa_maddv_df(DF_BYTE, pwd->b[8],  pws->b[8],  pwt->b[8]);
+    pwd->b[9]  = msa_maddv_df(DF_BYTE, pwd->b[9],  pws->b[9],  pwt->b[9]);
+    pwd->b[10] = msa_maddv_df(DF_BYTE, pwd->b[10], pws->b[10], pwt->b[10]);
+    pwd->b[11] = msa_maddv_df(DF_BYTE, pwd->b[11], pws->b[11], pwt->b[11]);
+    pwd->b[12] = msa_maddv_df(DF_BYTE, pwd->b[12], pws->b[12], pwt->b[12]);
+    pwd->b[13] = msa_maddv_df(DF_BYTE, pwd->b[13], pws->b[13], pwt->b[13]);
+    pwd->b[14] = msa_maddv_df(DF_BYTE, pwd->b[14], pws->b[14], pwt->b[14]);
+    pwd->b[15] = msa_maddv_df(DF_BYTE, pwd->b[15], pws->b[15], pwt->b[15]);
 }
 
 void helper_msa_maddv_h(CPUMIPSState *env,
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 03/33] target/mips: Fix MSA MSUBV.B opcode
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
  2021-10-23 21:47 ` [PATCH 01/33] tests/tcg: Fix some targets default cross compiler path Philippe Mathieu-Daudé
  2021-10-23 21:47 ` [PATCH 02/33] target/mips: Fix MSA MADDV.B opcode Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-23 21:47 ` [PATCH 04/33] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation Philippe Mathieu-Daudé
                   ` (30 subsequent siblings)
  33 siblings, 0 replies; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

The result of the 'Vector Multiply and Subtract' opcode is
incorrect with Byte vectors. Probably due to a copy/paste error,
commit 5f148a02327 mistakenly used the $wt (target register)
instead  of $wd (destination register) as first operand. Fix that.

Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Fixes: 5f148a02327 ("target/mips: msa: Split helpers for MSUBV.<B|H|W|D>")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa_helper.c | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
index d978909527f..5667b1f0a15 100644
--- a/target/mips/tcg/msa_helper.c
+++ b/target/mips/tcg/msa_helper.c
@@ -3303,22 +3303,22 @@ void helper_msa_msubv_b(CPUMIPSState *env,
     wr_t *pws = &(env->active_fpu.fpr[ws].wr);
     wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
 
-    pwd->b[0]  = msa_msubv_df(DF_BYTE, pwt->b[0],  pws->b[0],  pwt->b[0]);
-    pwd->b[1]  = msa_msubv_df(DF_BYTE, pwt->b[1],  pws->b[1],  pwt->b[1]);
-    pwd->b[2]  = msa_msubv_df(DF_BYTE, pwt->b[2],  pws->b[2],  pwt->b[2]);
-    pwd->b[3]  = msa_msubv_df(DF_BYTE, pwt->b[3],  pws->b[3],  pwt->b[3]);
-    pwd->b[4]  = msa_msubv_df(DF_BYTE, pwt->b[4],  pws->b[4],  pwt->b[4]);
-    pwd->b[5]  = msa_msubv_df(DF_BYTE, pwt->b[5],  pws->b[5],  pwt->b[5]);
-    pwd->b[6]  = msa_msubv_df(DF_BYTE, pwt->b[6],  pws->b[6],  pwt->b[6]);
-    pwd->b[7]  = msa_msubv_df(DF_BYTE, pwt->b[7],  pws->b[7],  pwt->b[7]);
-    pwd->b[8]  = msa_msubv_df(DF_BYTE, pwt->b[8],  pws->b[8],  pwt->b[8]);
-    pwd->b[9]  = msa_msubv_df(DF_BYTE, pwt->b[9],  pws->b[9],  pwt->b[9]);
-    pwd->b[10] = msa_msubv_df(DF_BYTE, pwt->b[10], pws->b[10], pwt->b[10]);
-    pwd->b[11] = msa_msubv_df(DF_BYTE, pwt->b[11], pws->b[11], pwt->b[11]);
-    pwd->b[12] = msa_msubv_df(DF_BYTE, pwt->b[12], pws->b[12], pwt->b[12]);
-    pwd->b[13] = msa_msubv_df(DF_BYTE, pwt->b[13], pws->b[13], pwt->b[13]);
-    pwd->b[14] = msa_msubv_df(DF_BYTE, pwt->b[14], pws->b[14], pwt->b[14]);
-    pwd->b[15] = msa_msubv_df(DF_BYTE, pwt->b[15], pws->b[15], pwt->b[15]);
+    pwd->b[0]  = msa_msubv_df(DF_BYTE, pwd->b[0],  pws->b[0],  pwt->b[0]);
+    pwd->b[1]  = msa_msubv_df(DF_BYTE, pwd->b[1],  pws->b[1],  pwt->b[1]);
+    pwd->b[2]  = msa_msubv_df(DF_BYTE, pwd->b[2],  pws->b[2],  pwt->b[2]);
+    pwd->b[3]  = msa_msubv_df(DF_BYTE, pwd->b[3],  pws->b[3],  pwt->b[3]);
+    pwd->b[4]  = msa_msubv_df(DF_BYTE, pwd->b[4],  pws->b[4],  pwt->b[4]);
+    pwd->b[5]  = msa_msubv_df(DF_BYTE, pwd->b[5],  pws->b[5],  pwt->b[5]);
+    pwd->b[6]  = msa_msubv_df(DF_BYTE, pwd->b[6],  pws->b[6],  pwt->b[6]);
+    pwd->b[7]  = msa_msubv_df(DF_BYTE, pwd->b[7],  pws->b[7],  pwt->b[7]);
+    pwd->b[8]  = msa_msubv_df(DF_BYTE, pwd->b[8],  pws->b[8],  pwt->b[8]);
+    pwd->b[9]  = msa_msubv_df(DF_BYTE, pwd->b[9],  pws->b[9],  pwt->b[9]);
+    pwd->b[10] = msa_msubv_df(DF_BYTE, pwd->b[10], pws->b[10], pwt->b[10]);
+    pwd->b[11] = msa_msubv_df(DF_BYTE, pwd->b[11], pws->b[11], pwt->b[11]);
+    pwd->b[12] = msa_msubv_df(DF_BYTE, pwd->b[12], pws->b[12], pwt->b[12]);
+    pwd->b[13] = msa_msubv_df(DF_BYTE, pwd->b[13], pws->b[13], pwt->b[13]);
+    pwd->b[14] = msa_msubv_df(DF_BYTE, pwd->b[14], pws->b[14], pwt->b[14]);
+    pwd->b[15] = msa_msubv_df(DF_BYTE, pwd->b[15], pws->b[15], pwt->b[15]);
 }
 
 void helper_msa_msubv_h(CPUMIPSState *env,
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 04/33] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (2 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 03/33] target/mips: Fix MSA MSUBV.B opcode Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-27 10:38   ` Philippe Mathieu-Daudé
  2021-10-23 21:47 ` [PATCH 05/33] target/mips: Have check_msa_access() return a boolean Philippe Mathieu-Daudé
                   ` (29 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
	Luis Pires, Alex Bennée

The following commits added various user-mode tests
for various MSA instructions:

 - 0fdd986a6c8 ("Add tests for MSA integer add instructions")
 - 1be82d89011 ("Add tests for MSA integer average instructions")
 - 1d336c87a3c ("Add tests for MSA bit set instructions")
 - 1e6bea794c8 ("Add tests for MSA integer max/min instructions")
 - 2a367db039f ("Add tests for MSA pack instructions")
 - 3d9569b8550 ("Add tests for MSA move instructions")
 - 4b302ce90db ("Add tests for MSA integer multiply instructions")
 - 520e210c0aa ("Add tests for MSA integer compare instructions")
 - 53e116fed6d ("Add tests for MSA integer subtract instructions")
 - 666952ea7c1 ("Add tests for MSA bit move instructions")
 - 72f463bc080 ("Add tests for MSA integer divide instructions")
 - 8598f5fac1c ("Add tests for MSA FP max/min instructions")
 - 99d423e576a ("Add tests for MSA shift instructions")
 - a8f91dd9fd0 ("Add tests for MSA integer dot product instructions")
 - b62592ab655 ("Add tests for MSA bit counting instructions")
 - ba632924450 ("Add tests for MSA logic instructions")
 - fc76f486677 ("Add tests for MSA interleave instructions")

Cover them in the buildsys machinery so they are run automatically
when calling 'make check-tcg'.

Start running them on the mips64el target.

Cc: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 tests/tcg/mips/ase-msa.mak         | 30 ++++++++++++++++++++++++++++++
 MAINTAINERS                        |  1 +
 tests/tcg/mips/Makefile.target     |  5 +++++
 tests/tcg/mips64/Makefile.target   |  9 +++++++++
 tests/tcg/mips64el/Makefile.target | 12 ++++++++++++
 tests/tcg/mipsel/Makefile.target   |  9 +++++++++
 6 files changed, 66 insertions(+)
 create mode 100644 tests/tcg/mips/ase-msa.mak
 create mode 100644 tests/tcg/mips64/Makefile.target
 create mode 100644 tests/tcg/mips64el/Makefile.target
 create mode 100644 tests/tcg/mipsel/Makefile.target

diff --git a/tests/tcg/mips/ase-msa.mak b/tests/tcg/mips/ase-msa.mak
new file mode 100644
index 00000000000..be1ba967a5b
--- /dev/null
+++ b/tests/tcg/mips/ase-msa.mak
@@ -0,0 +1,30 @@
+# -*- Mode: makefile -*-
+#
+# MIPS MSA specific TCG tests
+#
+# Copyright (c) 2021 Philippe Mathieu-Daudé <f4bug@amsat.org>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+MSA_DIR = $(SRC_PATH)/tests/tcg/mips/user/ase/msa
+
+MSA_TEST_CLASS = bit-count bit-move bit-set fixed-multiply \
+				float-max-min int-add int-average int-compare int-divide \
+				int-dot-product interleave int-max-min int-modulo \
+				int-multiply int-subtract logic move pack shift
+
+MSA_TEST_SRCS = $(foreach class,$(MSA_TEST_CLASS),$(wildcard $(MSA_DIR)/$(class)/*.c))
+
+MSA_TESTS = $(patsubst %.c,%,$(notdir $(MSA_TEST_SRCS)))
+
+$(MSA_TESTS): CFLAGS+=-mmsa $(MSA_CFLAGS)
+$(MSA_TESTS): %: $(foreach CLASS,$(MSA_TEST_CLASS),$(wildcard $(MSA_DIR)/$(CLASS)/%.c))
+	$(CC) -static $(CFLAGS) -o $@ \
+		$(foreach CLASS,$(MSA_TEST_CLASS),$(wildcard $(MSA_DIR)/$(CLASS)/$@.c))
+
+$(foreach test,$(MSA_TESTS),run-$(test)): QEMU_OPTS += -cpu $(MSA_CPU)
+
+# FIXME: These tests fail when using plugins
+ifneq ($(CONFIG_PLUGIN),y)
+TESTS += $(MSA_TESTS)
+endif
diff --git a/MAINTAINERS b/MAINTAINERS
index 4e77d03651b..53c6c549b80 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3111,6 +3111,7 @@ R: Jiaxun Yang <jiaxun.yang@flygoat.com>
 R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
 S: Odd Fixes
 F: tcg/mips/
+F: tests/tcg/mips*
 
 PPC TCG target
 M: Richard Henderson <richard.henderson@linaro.org>
diff --git a/tests/tcg/mips/Makefile.target b/tests/tcg/mips/Makefile.target
index 1a994d5525e..191fe179119 100644
--- a/tests/tcg/mips/Makefile.target
+++ b/tests/tcg/mips/Makefile.target
@@ -17,3 +17,8 @@ TESTS += $(MIPS_TESTS)
 hello-mips: CFLAGS+=-mno-abicalls -fno-PIC -mabi=32
 hello-mips: LDFLAGS+=-nostdlib
 endif
+
+# FIXME enable MSA tests
+#MSA_CFLAGS=-march=mips64r5 -mnan=2008
+#MSA_CPU=P5600
+#include $(SRC_PATH)/tests/tcg/mips/ase-msa.mak
diff --git a/tests/tcg/mips64/Makefile.target b/tests/tcg/mips64/Makefile.target
new file mode 100644
index 00000000000..d876b92f219
--- /dev/null
+++ b/tests/tcg/mips64/Makefile.target
@@ -0,0 +1,9 @@
+# -*- Mode: makefile -*-
+#
+# mips64el specific TCG tests
+#
+# Copyright (c) 2021 Philippe Mathieu-Daudé <f4bug@amsat.org>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# 64-bit MSA is tested on little-endian target
diff --git a/tests/tcg/mips64el/Makefile.target b/tests/tcg/mips64el/Makefile.target
new file mode 100644
index 00000000000..87c0d6dce18
--- /dev/null
+++ b/tests/tcg/mips64el/Makefile.target
@@ -0,0 +1,12 @@
+# -*- Mode: makefile -*-
+#
+# mips64el specific TCG tests
+#
+# Copyright (c) 2021 Philippe Mathieu-Daudé <f4bug@amsat.org>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# MSA
+MSA_CFLAGS=-march=mips64r5 -mnan=legacy
+MSA_CPU=Loongson-3A4000
+include $(SRC_PATH)/tests/tcg/mips/ase-msa.mak
diff --git a/tests/tcg/mipsel/Makefile.target b/tests/tcg/mipsel/Makefile.target
new file mode 100644
index 00000000000..c8acacb4497
--- /dev/null
+++ b/tests/tcg/mipsel/Makefile.target
@@ -0,0 +1,9 @@
+# -*- Mode: makefile -*-
+#
+# mipsel specific TCG tests
+#
+# Copyright (c) 2021 Philippe Mathieu-Daudé <f4bug@amsat.org>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# 32-bit MSA is tested on big-endian target
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 05/33] target/mips: Have check_msa_access() return a boolean
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (3 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 04/33] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-24  1:02   ` Richard Henderson
  2021-10-23 21:47 ` [PATCH 06/33] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum Philippe Mathieu-Daudé
                   ` (28 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Have check_msa_access() return a boolean value so we can
return early if MSA is not enabled.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa_translate.c | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 3ef912da6b8..9e0a08fe335 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -293,19 +293,19 @@ void msa_translate_init(void)
     }
 }
 
-static inline int check_msa_access(DisasContext *ctx)
+static inline bool check_msa_access(DisasContext *ctx)
 {
     if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) &&
                  !(ctx->hflags & MIPS_HFLAG_F64))) {
         gen_reserved_instruction(ctx);
-        return 0;
+        return false;
     }
 
     if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) {
         generate_exception_end(ctx, EXCP_MSADIS);
-        return 0;
+        return false;
     }
-    return 1;
+    return true;
 }
 
 static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
@@ -354,7 +354,9 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond)
 {
     TCGv_i64 t0;
 
-    check_msa_access(ctx);
+    if (!check_msa_access(ctx)) {
+        return false;
+    }
 
     if (ctx->hflags & MIPS_HFLAG_BMASK) {
         gen_reserved_instruction(ctx);
@@ -386,7 +388,9 @@ static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a)
 
 static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
 {
-    check_msa_access(ctx);
+    if (!check_msa_access(ctx)) {
+        return false;
+    }
 
     if (ctx->hflags & MIPS_HFLAG_BMASK) {
         gen_reserved_instruction(ctx);
@@ -2158,7 +2162,9 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
 {
     uint32_t opcode = ctx->opcode;
 
-    check_msa_access(ctx);
+    if (!check_msa_access(ctx)) {
+        return false;
+    }
 
     switch (MASK_MSA_MINOR(opcode)) {
     case OPC_MSA_I8_00:
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 06/33] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (4 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 05/33] target/mips: Have check_msa_access() return a boolean Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-24  1:03   ` Richard Henderson
  2021-10-23 21:47 ` [PATCH 07/33] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v Philippe Mathieu-Daudé
                   ` (27 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Replace magic DataFormat value by the corresponding
enum from CPUMIPSMSADataFormat.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa_translate.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 9e0a08fe335..1c4a802ff55 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -1801,10 +1801,10 @@ static void gen_msa_3rf(DisasContext *ctx)
     case OPC_MULR_Q_df:
     case OPC_MADDR_Q_df:
     case OPC_MSUBR_Q_df:
-        tdf = tcg_constant_i32(df + 1);
+        tdf = tcg_constant_i32(DF_HALF + df);
         break;
     default:
-        tdf = tcg_constant_i32(df + 2);
+        tdf = tcg_constant_i32(DF_WORD + df);
         break;
     }
 
@@ -2033,7 +2033,7 @@ static void gen_msa_2rf(DisasContext *ctx)
     TCGv_i32 twd = tcg_const_i32(wd);
     TCGv_i32 tws = tcg_const_i32(ws);
     /* adjust df value for floating-point instruction */
-    TCGv_i32 tdf = tcg_constant_i32(df + 2);
+    TCGv_i32 tdf = tcg_constant_i32(DF_WORD + df);
 
     switch (MASK_MSA_2RF(ctx->opcode)) {
     case OPC_FCLASS_df:
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 07/33] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (5 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 06/33] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-24  1:05   ` Richard Henderson
  2021-10-23 21:47 ` [PATCH 08/33] target/mips: Convert MSA LDI opcode to decodetree Philippe Mathieu-Daudé
                   ` (26 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

This 'shift amount' format is not always 16-bit, so name it
generically as 'sa'. This will help to unify the various
arg_msa decodetree generated structures.

Rename the @bz format -> @bz_v (specific @bz with df=3) and
@bz_df -> @bz (generic @bz).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      | 15 +++++++--------
 target/mips/tcg/msa_translate.c | 20 ++++++++++----------
 2 files changed, 17 insertions(+), 18 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 74d99f6862c..aa784cf12a9 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -13,19 +13,18 @@
 
 &r                  rs rt rd sa
 
-&msa_bz             df wt s16
+&msa_bz             df       wt sa
 
 @lsa                ...... rs:5 rt:5 rd:5 ... sa:2 ......   &r
-@bz                 ...... ... ..   wt:5 s16:16             &msa_bz df=3
-@bz_df              ...... ... df:2 wt:5 s16:16             &msa_bz
+@bz_v               ...... ... ..    wt:5 sa:16             &msa_bz df=3
+@bz                 ...... ...  df:2 wt:5 sa:16             &msa_bz
 
 LSA                 000000 ..... ..... ..... 000 .. 000101  @lsa
 DLSA                000000 ..... ..... ..... 000 .. 010101  @lsa
 
-BZ_V                010001 01011  ..... ................    @bz
-BNZ_V               010001 01111  ..... ................    @bz
-
-BZ_x                010001 110 .. ..... ................    @bz_df
-BNZ_x               010001 111 .. ..... ................    @bz_df
+BZ_V                010001 01011  ..... ................    @bz_v
+BNZ_V               010001 01111  ..... ................    @bz_v
+BZ                  010001 110 .. ..... ................    @bz
+BNZ                 010001 111 .. ..... ................    @bz
 
 MSA                 011110 --------------------------
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 1c4a802ff55..c2a48aecc46 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -350,7 +350,7 @@ static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
     tcg_temp_free_i64(t1);
 }
 
-static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond)
+static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int sa, TCGCond cond)
 {
     TCGv_i64 t0;
 
@@ -368,7 +368,7 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond)
     tcg_gen_trunc_i64_tl(bcond, t0);
     tcg_temp_free_i64(t0);
 
-    ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
+    ctx->btarget = ctx->base.pc_next + (sa << 2) + 4;
 
     ctx->hflags |= MIPS_HFLAG_BC;
     ctx->hflags |= MIPS_HFLAG_BDS32;
@@ -378,15 +378,15 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond)
 
 static bool trans_BZ_V(DisasContext *ctx, arg_msa_bz *a)
 {
-    return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_EQ);
+    return gen_msa_BxZ_V(ctx, a->wt, a->sa, TCG_COND_EQ);
 }
 
 static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a)
 {
-    return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_NE);
+    return gen_msa_BxZ_V(ctx, a->wt, a->sa, TCG_COND_NE);
 }
 
-static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
+static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int sa, bool if_not)
 {
     if (!check_msa_access(ctx)) {
         return false;
@@ -399,21 +399,21 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
 
     gen_check_zero_element(bcond, df, wt, if_not ? TCG_COND_EQ : TCG_COND_NE);
 
-    ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
+    ctx->btarget = ctx->base.pc_next + (sa << 2) + 4;
     ctx->hflags |= MIPS_HFLAG_BC;
     ctx->hflags |= MIPS_HFLAG_BDS32;
 
     return true;
 }
 
-static bool trans_BZ_x(DisasContext *ctx, arg_msa_bz *a)
+static bool trans_BZ(DisasContext *ctx, arg_msa_bz *a)
 {
-    return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, false);
+    return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, false);
 }
 
-static bool trans_BNZ_x(DisasContext *ctx, arg_msa_bz *a)
+static bool trans_BNZ(DisasContext *ctx, arg_msa_bz *a)
 {
-    return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, true);
+    return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, true);
 }
 
 static void gen_msa_i8(DisasContext *ctx)
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 08/33] target/mips: Convert MSA LDI opcode to decodetree
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (6 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 07/33] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-24  1:53   ` Richard Henderson
  2021-10-23 21:47 ` [PATCH 09/33] target/mips: Introduce generic TRANS_CHECK() for decodetree helpers Philippe Mathieu-Daudé
                   ` (25 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Convert the LDI opcode (Immediate Load) to decodetree. Since it
overlaps with the generic MSA handler, use a decodetree overlap
group.

Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      |  8 +++++++-
 target/mips/tcg/msa_translate.c | 30 ++++++++++++++++++++++--------
 2 files changed, 29 insertions(+), 9 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index aa784cf12a9..86aa66f05b9 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -14,10 +14,12 @@
 &r                  rs rt rd sa
 
 &msa_bz             df       wt sa
+&msa_ldst           df wd ws    sa
 
 @lsa                ...... rs:5 rt:5 rd:5 ... sa:2 ......   &r
 @bz_v               ...... ... ..    wt:5 sa:16             &msa_bz df=3
 @bz                 ...... ...  df:2 wt:5 sa:16             &msa_bz
+@ldi                ...... ... df:2 sa:s10     wd:5 ......  &msa_ldst ws=0
 
 LSA                 000000 ..... ..... ..... 000 .. 000101  @lsa
 DLSA                000000 ..... ..... ..... 000 .. 010101  @lsa
@@ -27,4 +29,8 @@ BNZ_V               010001 01111  ..... ................    @bz_v
 BZ                  010001 110 .. ..... ................    @bz
 BNZ                 010001 111 .. ..... ................    @bz
 
-MSA                 011110 --------------------------
+{
+  LDI               011110 110 .. ..........  ..... 000111  @ldi
+
+  MSA               011110 --------------------------
+}
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index c2a48aecc46..3b0dfcca69d 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -70,7 +70,6 @@ enum {
     OPC_CLEI_S_df   = (0x4 << 23) | OPC_MSA_I5_07,
     OPC_MINI_U_df   = (0x5 << 23) | OPC_MSA_I5_06,
     OPC_CLEI_U_df   = (0x5 << 23) | OPC_MSA_I5_07,
-    OPC_LDI_df      = (0x6 << 23) | OPC_MSA_I5_07,
 
     /* I8 instruction */
     OPC_ANDI_B      = (0x0 << 24) | OPC_MSA_I8_00,
@@ -525,13 +524,6 @@ static void gen_msa_i5(DisasContext *ctx)
     case OPC_CLEI_U_df:
         gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm);
         break;
-    case OPC_LDI_df:
-        {
-            int32_t s10 = sextract32(ctx->opcode, 11, 10);
-            tcg_gen_movi_i32(timm, s10);
-            gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm);
-        }
-        break;
     default:
         MIPS_INVAL("MSA instruction");
         gen_reserved_instruction(ctx);
@@ -544,6 +536,28 @@ static void gen_msa_i5(DisasContext *ctx)
     tcg_temp_free_i32(timm);
 }
 
+static bool trans_LDI(DisasContext *ctx, arg_msa_ldst *a)
+{
+    TCGv_i32 tdf;
+    TCGv_i32 twd;
+    TCGv_i32 timm;
+
+    if (!check_msa_access(ctx)) {
+        return false;
+    }
+
+    tdf = tcg_constant_i32(a->df);
+    twd = tcg_const_i32(a->wd);
+    timm = tcg_const_i32(a->sa);
+
+    gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm);
+
+    tcg_temp_free_i32(twd);
+    tcg_temp_free_i32(timm);
+
+    return true;
+}
+
 static void gen_msa_bit(DisasContext *ctx)
 {
 #define MASK_MSA_BIT(op)    (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 09/33] target/mips: Introduce generic TRANS_CHECK() for decodetree helpers
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (7 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 08/33] target/mips: Convert MSA LDI opcode to decodetree Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-24  1:58   ` Richard Henderson
  2021-10-23 21:47 ` [PATCH 10/33] target/mips: Extract df_extract() helper Philippe Mathieu-Daudé
                   ` (24 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Similar to the TRANS() macro introduced in commit fb3164e412d,
introduce TRANS_CHECK() which takes a boolean expression as
argument.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/translate.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index 6111493651f..3ef09cc50c9 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -224,6 +224,15 @@ bool decode_ext_vr54xx(DisasContext *ctx, uint32_t insn);
     static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
     { return FUNC(ctx, a, __VA_ARGS__); }
 
+#define TRANS_CHECK(NAME, CHECK_EXPR, FUNC, ...) \
+    static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+    { \
+        if (!(CHECK_EXPR)) { \
+            return false; \
+        } \
+        return FUNC(ctx, a, __VA_ARGS__); \
+    }
+
 static inline bool cpu_is_bigendian(DisasContext *ctx)
 {
     return extract32(ctx->CP0_Config0, CP0C0_BE, 1);
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 10/33] target/mips: Extract df_extract() helper
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (8 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 09/33] target/mips: Introduce generic TRANS_CHECK() for decodetree helpers Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-24  2:26   ` Richard Henderson
  2021-10-23 21:47 ` [PATCH 11/33] target/mips: Convert MSA I5 instruction format to decodetree Philippe Mathieu-Daudé
                   ` (23 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Extract the common code which parses data formats to an helper.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa_translate.c | 68 +++++++++++++++++++--------------
 1 file changed, 39 insertions(+), 29 deletions(-)

diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 3b0dfcca69d..7c1bbfaec61 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -272,6 +272,40 @@ static const char msaregnames[][6] = {
     "w30.d0", "w30.d1", "w31.d0", "w31.d1",
 };
 
+/* Encoding of Operation Field */
+static const struct dfe {
+    enum CPUMIPSMSADataFormat df;
+    int start;
+    int length;
+    uint32_t value;
+} df_elm[] = {
+    /* Table 3.26 ELM Instruction Format */
+    {DF_BYTE,   4, 2, 0b00},
+    {DF_HALF,   3, 3, 0b100},
+    {DF_WORD,   2, 4, 0b1100},
+    {DF_DOUBLE, 1, 5, 0b11100}
+}, df_bit[] = {
+    /* Table 3.28 BIT Instruction Format */
+    {DF_BYTE,   3, 4, 0b1110},
+    {DF_HALF,   4, 3, 0b110},
+    {DF_WORD,   5, 2, 0b10},
+    {DF_DOUBLE, 6, 1, 0b0}
+};
+
+/* Extract Operation Field (used by ELM & BIT instructions) */
+static bool df_extract(const struct dfe *s, int value,
+                       enum CPUMIPSMSADataFormat *df, uint32_t *x)
+{
+    for (unsigned i = 0; i < 4; i++) {
+        if (extract32(value, s->start, s->length) == s->value) {
+            *x = extract32(value, 0, s->start);
+            *df = s->df;
+            return true;
+        }
+    }
+    return false;
+}
+
 static TCGv_i64 msa_wr_d[64];
 
 void msa_translate_init(void)
@@ -562,7 +596,6 @@ static void gen_msa_bit(DisasContext *ctx)
 {
 #define MASK_MSA_BIT(op)    (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
     uint8_t dfm = (ctx->opcode >> 16) & 0x7f;
-    uint32_t df = 0, m = 0;
     uint8_t ws = (ctx->opcode >> 11) & 0x1f;
     uint8_t wd = (ctx->opcode >> 6) & 0x1f;
 
@@ -570,20 +603,9 @@ static void gen_msa_bit(DisasContext *ctx)
     TCGv_i32 tm;
     TCGv_i32 twd;
     TCGv_i32 tws;
+    uint32_t df, m;
 
-    if ((dfm & 0x40) == 0x00) {
-        m = dfm & 0x3f;
-        df = DF_DOUBLE;
-    } else if ((dfm & 0x60) == 0x40) {
-        m = dfm & 0x1f;
-        df = DF_WORD;
-    } else if ((dfm & 0x70) == 0x60) {
-        m = dfm & 0x0f;
-        df = DF_HALF;
-    } else if ((dfm & 0x78) == 0x70) {
-        m = dfm & 0x7;
-        df = DF_BYTE;
-    } else {
+    if (!df_extract(df_bit, dfm, &df, &m)) {
         gen_reserved_instruction(ctx);
         return;
     }
@@ -1768,25 +1790,13 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
 static void gen_msa_elm(DisasContext *ctx)
 {
     uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
-    uint32_t df = 0, n = 0;
+    uint32_t df, n;
 
-    if ((dfn & 0x30) == 0x00) {
-        n = dfn & 0x0f;
-        df = DF_BYTE;
-    } else if ((dfn & 0x38) == 0x20) {
-        n = dfn & 0x07;
-        df = DF_HALF;
-    } else if ((dfn & 0x3c) == 0x30) {
-        n = dfn & 0x03;
-        df = DF_WORD;
-    } else if ((dfn & 0x3e) == 0x38) {
-        n = dfn & 0x01;
-        df = DF_DOUBLE;
-    } else if (dfn == 0x3E) {
+    if (dfn == 0x3E) {
         /* CTCMSA, CFCMSA, MOVE.V */
         gen_msa_elm_3e(ctx);
         return;
-    } else {
+    } else if (!df_extract(df_elm, dfn, &df, &n)) {
         gen_reserved_instruction(ctx);
         return;
     }
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 11/33] target/mips: Convert MSA I5 instruction format to decodetree
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (9 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 10/33] target/mips: Extract df_extract() helper Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-24  2:10   ` Richard Henderson
  2021-10-23 21:47 ` [PATCH 12/33] target/mips: Convert MSA BIT " Philippe Mathieu-Daudé
                   ` (22 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Convert instructions with a 5-bit immediate value to decodetree.

Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      | 15 +++++
 target/mips/tcg/msa_translate.c | 99 +++++++++------------------------
 2 files changed, 40 insertions(+), 74 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 86aa66f05b9..5aaa85456da 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -19,6 +19,8 @@
 @lsa                ...... rs:5 rt:5 rd:5 ... sa:2 ......   &r
 @bz_v               ...... ... ..    wt:5 sa:16             &msa_bz df=3
 @bz                 ...... ...  df:2 wt:5 sa:16             &msa_bz
+@u5                 ...... ... df:2 sa:5  ws:5 wd:5 ......  &msa_ldst
+@s5                 ...... ... df:2 sa:s5 ws:5 wd:5 ......  &msa_ldst
 @ldi                ...... ... df:2 sa:s10     wd:5 ......  &msa_ldst ws=0
 
 LSA                 000000 ..... ..... ..... 000 .. 000101  @lsa
@@ -30,6 +32,19 @@ BZ                  010001 110 .. ..... ................    @bz
 BNZ                 010001 111 .. ..... ................    @bz
 
 {
+  ADDVI             011110 000 .. ..... ..... ..... 000110  @u5
+  SUBVI             011110 001 .. ..... ..... ..... 000110  @u5
+  MAXI_S            011110 010 .. ..... ..... ..... 000110  @s5
+  MAXI_U            011110 011 .. ..... ..... ..... 000110  @u5
+  MINI_S            011110 100 .. ..... ..... ..... 000110  @s5
+  MINI_U            011110 101 .. ..... ..... ..... 000110  @u5
+
+  CEQI              011110 000 .. ..... ..... ..... 000111  @s5
+  CLTI_S            011110 010 .. ..... ..... ..... 000111  @s5
+  CLTI_U            011110 011 .. ..... ..... ..... 000111  @u5
+  CLEI_S            011110 100 .. ..... ..... ..... 000111  @s5
+  CLEI_U            011110 101 .. ..... ..... ..... 000111  @u5
+
   LDI               011110 110 .. ..........  ..... 000111  @ldi
 
   MSA               011110 --------------------------
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 7c1bbfaec61..962aef601cb 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -27,8 +27,6 @@ enum {
     OPC_MSA_I8_00   = 0x00 | OPC_MSA,
     OPC_MSA_I8_01   = 0x01 | OPC_MSA,
     OPC_MSA_I8_02   = 0x02 | OPC_MSA,
-    OPC_MSA_I5_06   = 0x06 | OPC_MSA,
-    OPC_MSA_I5_07   = 0x07 | OPC_MSA,
     OPC_MSA_BIT_09  = 0x09 | OPC_MSA,
     OPC_MSA_BIT_0A  = 0x0A | OPC_MSA,
     OPC_MSA_3R_0D   = 0x0D | OPC_MSA,
@@ -58,19 +56,6 @@ enum {
 };
 
 enum {
-    /* I5 instruction df(bits 22..21) = _b, _h, _w, _d */
-    OPC_ADDVI_df    = (0x0 << 23) | OPC_MSA_I5_06,
-    OPC_CEQI_df     = (0x0 << 23) | OPC_MSA_I5_07,
-    OPC_SUBVI_df    = (0x1 << 23) | OPC_MSA_I5_06,
-    OPC_MAXI_S_df   = (0x2 << 23) | OPC_MSA_I5_06,
-    OPC_CLTI_S_df   = (0x2 << 23) | OPC_MSA_I5_07,
-    OPC_MAXI_U_df   = (0x3 << 23) | OPC_MSA_I5_06,
-    OPC_CLTI_U_df   = (0x3 << 23) | OPC_MSA_I5_07,
-    OPC_MINI_S_df   = (0x4 << 23) | OPC_MSA_I5_06,
-    OPC_CLEI_S_df   = (0x4 << 23) | OPC_MSA_I5_07,
-    OPC_MINI_U_df   = (0x5 << 23) | OPC_MSA_I5_06,
-    OPC_CLEI_U_df   = (0x5 << 23) | OPC_MSA_I5_07,
-
     /* I8 instruction */
     OPC_ANDI_B      = (0x0 << 24) | OPC_MSA_I8_00,
     OPC_BMNZI_B     = (0x0 << 24) | OPC_MSA_I8_01,
@@ -341,6 +326,9 @@ static inline bool check_msa_access(DisasContext *ctx)
     return true;
 }
 
+#define TRANS_MSA(NAME, trans_func, gen_func) \
+        TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, gen_func)
+
 static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
                                    TCGCond cond)
 {
@@ -507,69 +495,36 @@ static void gen_msa_i8(DisasContext *ctx)
     tcg_temp_free_i32(ti8);
 }
 
-static void gen_msa_i5(DisasContext *ctx)
+static bool trans_msa_i5(DisasContext *ctx, arg_msa_ldst *a,
+                         void (*gen_msa_i5)(TCGv_ptr, TCGv_i32, TCGv_i32,
+                                            TCGv_i32, TCGv_i32))
 {
-#define MASK_MSA_I5(op)    (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
-    int8_t s5 = (int8_t) sextract32(ctx->opcode, 16, 5);
-    uint8_t u5 = extract32(ctx->opcode, 16, 5);
+    TCGv_i32 tdf = tcg_constant_i32(a->df);
+    TCGv_i32 twd = tcg_const_i32(a->wd);
+    TCGv_i32 tws = tcg_const_i32(a->ws);
+    TCGv_i32 timm = tcg_const_i32(a->sa);
 
-    TCGv_i32 tdf = tcg_const_i32(extract32(ctx->opcode, 21, 2));
-    TCGv_i32 twd = tcg_const_i32(extract32(ctx->opcode, 11, 5));
-    TCGv_i32 tws = tcg_const_i32(extract32(ctx->opcode, 6, 5));
-    TCGv_i32 timm = tcg_temp_new_i32();
-    tcg_gen_movi_i32(timm, u5);
+    gen_msa_i5(cpu_env, tdf, twd, tws, timm);
 
-    switch (MASK_MSA_I5(ctx->opcode)) {
-    case OPC_ADDVI_df:
-        gen_helper_msa_addvi_df(cpu_env, tdf, twd, tws, timm);
-        break;
-    case OPC_SUBVI_df:
-        gen_helper_msa_subvi_df(cpu_env, tdf, twd, tws, timm);
-        break;
-    case OPC_MAXI_S_df:
-        tcg_gen_movi_i32(timm, s5);
-        gen_helper_msa_maxi_s_df(cpu_env, tdf, twd, tws, timm);
-        break;
-    case OPC_MAXI_U_df:
-        gen_helper_msa_maxi_u_df(cpu_env, tdf, twd, tws, timm);
-        break;
-    case OPC_MINI_S_df:
-        tcg_gen_movi_i32(timm, s5);
-        gen_helper_msa_mini_s_df(cpu_env, tdf, twd, tws, timm);
-        break;
-    case OPC_MINI_U_df:
-        gen_helper_msa_mini_u_df(cpu_env, tdf, twd, tws, timm);
-        break;
-    case OPC_CEQI_df:
-        tcg_gen_movi_i32(timm, s5);
-        gen_helper_msa_ceqi_df(cpu_env, tdf, twd, tws, timm);
-        break;
-    case OPC_CLTI_S_df:
-        tcg_gen_movi_i32(timm, s5);
-        gen_helper_msa_clti_s_df(cpu_env, tdf, twd, tws, timm);
-        break;
-    case OPC_CLTI_U_df:
-        gen_helper_msa_clti_u_df(cpu_env, tdf, twd, tws, timm);
-        break;
-    case OPC_CLEI_S_df:
-        tcg_gen_movi_i32(timm, s5);
-        gen_helper_msa_clei_s_df(cpu_env, tdf, twd, tws, timm);
-        break;
-    case OPC_CLEI_U_df:
-        gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm);
-        break;
-    default:
-        MIPS_INVAL("MSA instruction");
-        gen_reserved_instruction(ctx);
-        break;
-    }
-
-    tcg_temp_free_i32(tdf);
     tcg_temp_free_i32(twd);
     tcg_temp_free_i32(tws);
     tcg_temp_free_i32(timm);
+
+    return true;
 }
 
+TRANS_MSA(ADDVI,    trans_msa_i5, gen_helper_msa_addvi_df);
+TRANS_MSA(SUBVI,    trans_msa_i5, gen_helper_msa_subvi_df);
+TRANS_MSA(MAXI_S,   trans_msa_i5, gen_helper_msa_maxi_s_df);
+TRANS_MSA(MAXI_U,   trans_msa_i5, gen_helper_msa_maxi_u_df);
+TRANS_MSA(MINI_S,   trans_msa_i5, gen_helper_msa_mini_s_df);
+TRANS_MSA(MINI_U,   trans_msa_i5, gen_helper_msa_mini_u_df);
+TRANS_MSA(CLTI_S,   trans_msa_i5, gen_helper_msa_clti_s_df);
+TRANS_MSA(CLTI_U,   trans_msa_i5, gen_helper_msa_clti_u_df);
+TRANS_MSA(CLEI_S,   trans_msa_i5, gen_helper_msa_clei_s_df);
+TRANS_MSA(CLEI_U,   trans_msa_i5, gen_helper_msa_clei_u_df);
+TRANS_MSA(CEQI,     trans_msa_i5, gen_helper_msa_ceqi_df);
+
 static bool trans_LDI(DisasContext *ctx, arg_msa_ldst *a)
 {
     TCGv_i32 tdf;
@@ -2196,10 +2151,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
     case OPC_MSA_I8_02:
         gen_msa_i8(ctx);
         break;
-    case OPC_MSA_I5_06:
-    case OPC_MSA_I5_07:
-        gen_msa_i5(ctx);
-        break;
     case OPC_MSA_BIT_09:
     case OPC_MSA_BIT_0A:
         gen_msa_bit(ctx);
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 12/33] target/mips: Convert MSA BIT instruction format to decodetree
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (10 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 11/33] target/mips: Convert MSA I5 instruction format to decodetree Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-24  2:45   ` Richard Henderson
  2021-10-23 21:47 ` [PATCH 13/33] target/mips: Convert MSA SHF opcode " Philippe Mathieu-Daudé
                   ` (21 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Convert instructions with an immediate bit index and
data format df/m to decodetree.

Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      | 15 +++++
 target/mips/tcg/msa_translate.c | 98 ++++++++-------------------------
 2 files changed, 39 insertions(+), 74 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 5aaa85456da..91d71ff560c 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -22,6 +22,7 @@
 @u5                 ...... ... df:2 sa:5  ws:5 wd:5 ......  &msa_ldst
 @s5                 ...... ... df:2 sa:s5 ws:5 wd:5 ......  &msa_ldst
 @ldi                ...... ... df:2 sa:s10     wd:5 ......  &msa_ldst ws=0
+@bit                ...... ... df:7       ws:5 wd:5 ......  &msa_ldst sa=0
 
 LSA                 000000 ..... ..... ..... 000 .. 000101  @lsa
 DLSA                000000 ..... ..... ..... 000 .. 010101  @lsa
@@ -47,5 +48,19 @@ BNZ                 010001 111 .. ..... ................    @bz
 
   LDI               011110 110 .. ..........  ..... 000111  @ldi
 
+  SLLI              011110 000 ....... ..... .....  001001  @bit
+  SRAI              011110 001 ....... ..... .....  001001  @bit
+  SRLI              011110 010 ....... ..... .....  001001  @bit
+  BCLRI             011110 011 ....... ..... .....  001001  @bit
+  BSETI             011110 100 ....... ..... .....  001001  @bit
+  BNEGI             011110 101 ....... ..... .....  001001  @bit
+  BINSLI            011110 110 ....... ..... .....  001001  @bit
+  BINSRI            011110 111 ....... ..... .....  001001  @bit
+
+  SAT_S             011110 000 ....... ..... .....  001010  @bit
+  SAT_U             011110 001 ....... ..... .....  001010  @bit
+  SRARI             011110 010 ....... ..... .....  001010  @bit
+  SRLRI             011110 011 ....... ..... .....  001010  @bit
+
   MSA               011110 --------------------------
 }
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 962aef601cb..10bbe25172a 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -27,8 +27,6 @@ enum {
     OPC_MSA_I8_00   = 0x00 | OPC_MSA,
     OPC_MSA_I8_01   = 0x01 | OPC_MSA,
     OPC_MSA_I8_02   = 0x02 | OPC_MSA,
-    OPC_MSA_BIT_09  = 0x09 | OPC_MSA,
-    OPC_MSA_BIT_0A  = 0x0A | OPC_MSA,
     OPC_MSA_3R_0D   = 0x0D | OPC_MSA,
     OPC_MSA_3R_0E   = 0x0E | OPC_MSA,
     OPC_MSA_3R_0F   = 0x0F | OPC_MSA,
@@ -222,20 +220,6 @@ enum {
     OPC_MSUBR_Q_df  = (0xE << 22) | OPC_MSA_3RF_1C,
     OPC_FSULE_df    = (0xF << 22) | OPC_MSA_3RF_1A,
     OPC_FMAX_A_df   = (0xF << 22) | OPC_MSA_3RF_1B,
-
-    /* BIT instruction df(bits 22..16) = _B _H _W _D */
-    OPC_SLLI_df     = (0x0 << 23) | OPC_MSA_BIT_09,
-    OPC_SAT_S_df    = (0x0 << 23) | OPC_MSA_BIT_0A,
-    OPC_SRAI_df     = (0x1 << 23) | OPC_MSA_BIT_09,
-    OPC_SAT_U_df    = (0x1 << 23) | OPC_MSA_BIT_0A,
-    OPC_SRLI_df     = (0x2 << 23) | OPC_MSA_BIT_09,
-    OPC_SRARI_df    = (0x2 << 23) | OPC_MSA_BIT_0A,
-    OPC_BCLRI_df    = (0x3 << 23) | OPC_MSA_BIT_09,
-    OPC_SRLRI_df    = (0x3 << 23) | OPC_MSA_BIT_0A,
-    OPC_BSETI_df    = (0x4 << 23) | OPC_MSA_BIT_09,
-    OPC_BNEGI_df    = (0x5 << 23) | OPC_MSA_BIT_09,
-    OPC_BINSLI_df   = (0x6 << 23) | OPC_MSA_BIT_09,
-    OPC_BINSRI_df   = (0x7 << 23) | OPC_MSA_BIT_09,
 };
 
 static const char msaregnames[][6] = {
@@ -547,78 +531,48 @@ static bool trans_LDI(DisasContext *ctx, arg_msa_ldst *a)
     return true;
 }
 
-static void gen_msa_bit(DisasContext *ctx)
+static bool trans_msa_bit(DisasContext *ctx, arg_msa_ldst *a,
+                          void (*gen_msa_bit)(TCGv_ptr, TCGv_i32, TCGv_i32,
+                                              TCGv_i32, TCGv_i32))
 {
-#define MASK_MSA_BIT(op)    (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
-    uint8_t dfm = (ctx->opcode >> 16) & 0x7f;
-    uint8_t ws = (ctx->opcode >> 11) & 0x1f;
-    uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-
     TCGv_i32 tdf;
     TCGv_i32 tm;
     TCGv_i32 twd;
     TCGv_i32 tws;
     uint32_t df, m;
 
-    if (!df_extract(df_bit, dfm, &df, &m)) {
+    if (!df_extract(df_bit, a->df, &df, &m)) {
         gen_reserved_instruction(ctx);
-        return;
+        return true;
     }
 
-    tdf = tcg_const_i32(df);
+    tdf = tcg_constant_i32(df);
     tm  = tcg_const_i32(m);
-    twd = tcg_const_i32(wd);
-    tws = tcg_const_i32(ws);
+    twd = tcg_const_i32(a->wd);
+    tws = tcg_const_i32(a->ws);
 
-    switch (MASK_MSA_BIT(ctx->opcode)) {
-    case OPC_SLLI_df:
-        gen_helper_msa_slli_df(cpu_env, tdf, twd, tws, tm);
-        break;
-    case OPC_SRAI_df:
-        gen_helper_msa_srai_df(cpu_env, tdf, twd, tws, tm);
-        break;
-    case OPC_SRLI_df:
-        gen_helper_msa_srli_df(cpu_env, tdf, twd, tws, tm);
-        break;
-    case OPC_BCLRI_df:
-        gen_helper_msa_bclri_df(cpu_env, tdf, twd, tws, tm);
-        break;
-    case OPC_BSETI_df:
-        gen_helper_msa_bseti_df(cpu_env, tdf, twd, tws, tm);
-        break;
-    case OPC_BNEGI_df:
-        gen_helper_msa_bnegi_df(cpu_env, tdf, twd, tws, tm);
-        break;
-    case OPC_BINSLI_df:
-        gen_helper_msa_binsli_df(cpu_env, tdf, twd, tws, tm);
-        break;
-    case OPC_BINSRI_df:
-        gen_helper_msa_binsri_df(cpu_env, tdf, twd, tws, tm);
-        break;
-    case OPC_SAT_S_df:
-        gen_helper_msa_sat_s_df(cpu_env, tdf, twd, tws, tm);
-        break;
-    case OPC_SAT_U_df:
-        gen_helper_msa_sat_u_df(cpu_env, tdf, twd, tws, tm);
-        break;
-    case OPC_SRARI_df:
-        gen_helper_msa_srari_df(cpu_env, tdf, twd, tws, tm);
-        break;
-    case OPC_SRLRI_df:
-        gen_helper_msa_srlri_df(cpu_env, tdf, twd, tws, tm);
-        break;
-    default:
-        MIPS_INVAL("MSA instruction");
-        gen_reserved_instruction(ctx);
-        break;
-    }
+    gen_msa_bit(cpu_env, tdf, twd, tws, tm);
 
-    tcg_temp_free_i32(tdf);
     tcg_temp_free_i32(tm);
     tcg_temp_free_i32(twd);
     tcg_temp_free_i32(tws);
+
+    return true;
 }
 
+TRANS_MSA(SLLI,     trans_msa_bit, gen_helper_msa_slli_df);
+TRANS_MSA(SRAI,     trans_msa_bit, gen_helper_msa_srai_df);
+TRANS_MSA(SRLI,     trans_msa_bit, gen_helper_msa_srli_df);
+TRANS_MSA(BCLRI,    trans_msa_bit, gen_helper_msa_bclri_df);
+TRANS_MSA(BSETI,    trans_msa_bit, gen_helper_msa_bseti_df);
+TRANS_MSA(BNEGI,    trans_msa_bit, gen_helper_msa_bnegi_df);
+TRANS_MSA(BINSLI,   trans_msa_bit, gen_helper_msa_binsli_df);
+TRANS_MSA(BINSRI,   trans_msa_bit, gen_helper_msa_binsri_df);
+TRANS_MSA(SAT_S,    trans_msa_bit, gen_helper_msa_sat_u_df);
+TRANS_MSA(SAT_U,    trans_msa_bit, gen_helper_msa_sat_u_df);
+TRANS_MSA(SRARI,    trans_msa_bit, gen_helper_msa_srari_df);
+TRANS_MSA(SRLRI,    trans_msa_bit, gen_helper_msa_srlri_df);
+
 static void gen_msa_3r(DisasContext *ctx)
 {
 #define MASK_MSA_3R(op)    (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
@@ -2151,10 +2105,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
     case OPC_MSA_I8_02:
         gen_msa_i8(ctx);
         break;
-    case OPC_MSA_BIT_09:
-    case OPC_MSA_BIT_0A:
-        gen_msa_bit(ctx);
-        break;
     case OPC_MSA_3R_0D:
     case OPC_MSA_3R_0E:
     case OPC_MSA_3R_0F:
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 13/33] target/mips: Convert MSA SHF opcode to decodetree
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (11 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 12/33] target/mips: Convert MSA BIT " Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-24  3:40   ` Richard Henderson
  2021-10-23 21:47 ` [PATCH 14/33] target/mips: Convert MSA I8 instruction format " Philippe Mathieu-Daudé
                   ` (20 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Convert the SHF opcode (Immediate Set Shuffle Elements) to decodetree.

Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      |  3 +++
 target/mips/tcg/msa_translate.c | 47 +++++++++++++++++++++------------
 2 files changed, 33 insertions(+), 17 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 91d71ff560c..6347468a709 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -22,6 +22,7 @@
 @u5                 ...... ... df:2 sa:5  ws:5 wd:5 ......  &msa_ldst
 @s5                 ...... ... df:2 sa:s5 ws:5 wd:5 ......  &msa_ldst
 @ldi                ...... ... df:2 sa:s10     wd:5 ......  &msa_ldst ws=0
+@i8_df              ......     df:2 sa:s8 ws:5 wd:5 ......  &msa_ldst
 @bit                ...... ... df:7       ws:5 wd:5 ......  &msa_ldst sa=0
 
 LSA                 000000 ..... ..... ..... 000 .. 000101  @lsa
@@ -33,6 +34,8 @@ BZ                  010001 110 .. ..... ................    @bz
 BNZ                 010001 111 .. ..... ................    @bz
 
 {
+  SHF               011110 .. ........ ..... .....  000010  @i8_df
+
   ADDVI             011110 000 .. ..... ..... ..... 000110  @u5
   SUBVI             011110 001 .. ..... ..... ..... 000110  @u5
   MAXI_S            011110 010 .. ..... ..... ..... 000110  @s5
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 10bbe25172a..7cb078bfe92 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -57,13 +57,10 @@ enum {
     /* I8 instruction */
     OPC_ANDI_B      = (0x0 << 24) | OPC_MSA_I8_00,
     OPC_BMNZI_B     = (0x0 << 24) | OPC_MSA_I8_01,
-    OPC_SHF_B       = (0x0 << 24) | OPC_MSA_I8_02,
     OPC_ORI_B       = (0x1 << 24) | OPC_MSA_I8_00,
     OPC_BMZI_B      = (0x1 << 24) | OPC_MSA_I8_01,
-    OPC_SHF_H       = (0x1 << 24) | OPC_MSA_I8_02,
     OPC_NORI_B      = (0x2 << 24) | OPC_MSA_I8_00,
     OPC_BSELI_B     = (0x2 << 24) | OPC_MSA_I8_01,
-    OPC_SHF_W       = (0x2 << 24) | OPC_MSA_I8_02,
     OPC_XORI_B      = (0x3 << 24) | OPC_MSA_I8_00,
 
     /* VEC/2R/2RF instruction */
@@ -454,20 +451,6 @@ static void gen_msa_i8(DisasContext *ctx)
     case OPC_BSELI_B:
         gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8);
         break;
-    case OPC_SHF_B:
-    case OPC_SHF_H:
-    case OPC_SHF_W:
-        {
-            uint8_t df = (ctx->opcode >> 24) & 0x3;
-            if (df == DF_DOUBLE) {
-                gen_reserved_instruction(ctx);
-            } else {
-                TCGv_i32 tdf = tcg_const_i32(df);
-                gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8);
-                tcg_temp_free_i32(tdf);
-            }
-        }
-        break;
     default:
         MIPS_INVAL("MSA instruction");
         gen_reserved_instruction(ctx);
@@ -479,6 +462,36 @@ static void gen_msa_i8(DisasContext *ctx)
     tcg_temp_free_i32(ti8);
 }
 
+static bool trans_SHF(DisasContext *ctx, arg_msa_ldst *a)
+{
+    TCGv_i32 tdf;
+    TCGv_i32 twd;
+    TCGv_i32 tws;
+    TCGv_i32 timm;
+
+    if (a->df == DF_DOUBLE) {
+        gen_reserved_instruction(ctx);
+        return true;
+    }
+
+    if (!check_msa_access(ctx)) {
+        return false;
+    }
+
+    tdf = tcg_constant_i32(a->df);
+    twd = tcg_const_i32(a->wd);
+    tws = tcg_const_i32(a->ws);
+    timm = tcg_const_i32(a->sa);
+
+    gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, timm);
+
+    tcg_temp_free_i32(tws);
+    tcg_temp_free_i32(twd);
+    tcg_temp_free_i32(timm);
+
+    return true;
+}
+
 static bool trans_msa_i5(DisasContext *ctx, arg_msa_ldst *a,
                          void (*gen_msa_i5)(TCGv_ptr, TCGv_i32, TCGv_i32,
                                             TCGv_i32, TCGv_i32))
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 14/33] target/mips: Convert MSA I8 instruction format to decodetree
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (12 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 13/33] target/mips: Convert MSA SHF opcode " Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-24  3:45   ` Richard Henderson
  2021-10-23 21:47 ` [PATCH 15/33] target/mips: Convert MSA load/store " Philippe Mathieu-Daudé
                   ` (19 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Convert instructions with an 8-bit immediate value and either
implicit data format or data format df to decodetree.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      |  8 ++++
 target/mips/tcg/msa_translate.c | 72 +++++++++------------------------
 2 files changed, 26 insertions(+), 54 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 6347468a709..3dd07dced57 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -23,6 +23,7 @@
 @s5                 ...... ... df:2 sa:s5 ws:5 wd:5 ......  &msa_ldst
 @ldi                ...... ... df:2 sa:s10     wd:5 ......  &msa_ldst ws=0
 @i8_df              ......     df:2 sa:s8 ws:5 wd:5 ......  &msa_ldst
+@i8                 ...... ..       sa:s8 ws:5 wd:5 ......  &msa_ldst df=0
 @bit                ...... ... df:7       ws:5 wd:5 ......  &msa_ldst sa=0
 
 LSA                 000000 ..... ..... ..... 000 .. 000101  @lsa
@@ -34,6 +35,13 @@ BZ                  010001 110 .. ..... ................    @bz
 BNZ                 010001 111 .. ..... ................    @bz
 
 {
+  ANDI              011110 00 ........ ..... .....  000000  @i8
+  ORI               011110 01 ........ ..... .....  000000  @i8
+  NORI              011110 10 ........ ..... .....  000000  @i8
+  XORI              011110 11 ........ ..... .....  000000  @i8
+  BMNZI             011110 00 ........ ..... .....  000001  @i8
+  BMZI              011110 01 ........ ..... .....  000001  @i8
+  BSELI             011110 10 ........ ..... .....  000001  @i8
   SHF               011110 .. ........ ..... .....  000010  @i8_df
 
   ADDVI             011110 000 .. ..... ..... ..... 000110  @u5
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 7cb078bfe92..2866687635d 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -24,9 +24,6 @@
 
 #define MASK_MSA_MINOR(op)          (MASK_OP_MAJOR(op) | (op & 0x3F))
 enum {
-    OPC_MSA_I8_00   = 0x00 | OPC_MSA,
-    OPC_MSA_I8_01   = 0x01 | OPC_MSA,
-    OPC_MSA_I8_02   = 0x02 | OPC_MSA,
     OPC_MSA_3R_0D   = 0x0D | OPC_MSA,
     OPC_MSA_3R_0E   = 0x0E | OPC_MSA,
     OPC_MSA_3R_0F   = 0x0F | OPC_MSA,
@@ -54,15 +51,6 @@ enum {
 };
 
 enum {
-    /* I8 instruction */
-    OPC_ANDI_B      = (0x0 << 24) | OPC_MSA_I8_00,
-    OPC_BMNZI_B     = (0x0 << 24) | OPC_MSA_I8_01,
-    OPC_ORI_B       = (0x1 << 24) | OPC_MSA_I8_00,
-    OPC_BMZI_B      = (0x1 << 24) | OPC_MSA_I8_01,
-    OPC_NORI_B      = (0x2 << 24) | OPC_MSA_I8_00,
-    OPC_BSELI_B     = (0x2 << 24) | OPC_MSA_I8_01,
-    OPC_XORI_B      = (0x3 << 24) | OPC_MSA_I8_00,
-
     /* VEC/2R/2RF instruction */
     OPC_AND_V       = (0x00 << 21) | OPC_MSA_VEC,
     OPC_OR_V        = (0x01 << 21) | OPC_MSA_VEC,
@@ -418,50 +406,31 @@ static bool trans_BNZ(DisasContext *ctx, arg_msa_bz *a)
     return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, true);
 }
 
-static void gen_msa_i8(DisasContext *ctx)
+static bool trans_msa_i8(DisasContext *ctx, arg_msa_ldst *a,
+                         void (*gen_msa_i8)(TCGv_ptr, TCGv_i32,
+                                            TCGv_i32, TCGv_i32))
 {
-#define MASK_MSA_I8(op)    (MASK_MSA_MINOR(op) | (op & (0x03 << 24)))
-    uint8_t i8 = (ctx->opcode >> 16) & 0xff;
-    uint8_t ws = (ctx->opcode >> 11) & 0x1f;
-    uint8_t wd = (ctx->opcode >> 6) & 0x1f;
+    TCGv_i32 twd = tcg_const_i32(a->wd);
+    TCGv_i32 tws = tcg_const_i32(a->ws);
+    TCGv_i32 timm = tcg_const_i32(a->sa);
 
-    TCGv_i32 twd = tcg_const_i32(wd);
-    TCGv_i32 tws = tcg_const_i32(ws);
-    TCGv_i32 ti8 = tcg_const_i32(i8);
-
-    switch (MASK_MSA_I8(ctx->opcode)) {
-    case OPC_ANDI_B:
-        gen_helper_msa_andi_b(cpu_env, twd, tws, ti8);
-        break;
-    case OPC_ORI_B:
-        gen_helper_msa_ori_b(cpu_env, twd, tws, ti8);
-        break;
-    case OPC_NORI_B:
-        gen_helper_msa_nori_b(cpu_env, twd, tws, ti8);
-        break;
-    case OPC_XORI_B:
-        gen_helper_msa_xori_b(cpu_env, twd, tws, ti8);
-        break;
-    case OPC_BMNZI_B:
-        gen_helper_msa_bmnzi_b(cpu_env, twd, tws, ti8);
-        break;
-    case OPC_BMZI_B:
-        gen_helper_msa_bmzi_b(cpu_env, twd, tws, ti8);
-        break;
-    case OPC_BSELI_B:
-        gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8);
-        break;
-    default:
-        MIPS_INVAL("MSA instruction");
-        gen_reserved_instruction(ctx);
-        break;
-    }
+    gen_msa_i8(cpu_env, twd, tws, timm);
 
     tcg_temp_free_i32(twd);
     tcg_temp_free_i32(tws);
-    tcg_temp_free_i32(ti8);
+    tcg_temp_free_i32(timm);
+
+    return true;
 }
 
+TRANS_MSA(ANDI,     trans_msa_i8, gen_helper_msa_andi_b);
+TRANS_MSA(ORI,      trans_msa_i8, gen_helper_msa_ori_b);
+TRANS_MSA(NORI,     trans_msa_i8, gen_helper_msa_nori_b);
+TRANS_MSA(XORI,     trans_msa_i8, gen_helper_msa_xori_b);
+TRANS_MSA(BMNZI,    trans_msa_i8, gen_helper_msa_bmnzi_b);
+TRANS_MSA(BMZI,     trans_msa_i8, gen_helper_msa_bmzi_b);
+TRANS_MSA(BSELI,    trans_msa_i8, gen_helper_msa_bseli_b);
+
 static bool trans_SHF(DisasContext *ctx, arg_msa_ldst *a)
 {
     TCGv_i32 tdf;
@@ -2113,11 +2082,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
     }
 
     switch (MASK_MSA_MINOR(opcode)) {
-    case OPC_MSA_I8_00:
-    case OPC_MSA_I8_01:
-    case OPC_MSA_I8_02:
-        gen_msa_i8(ctx);
-        break;
     case OPC_MSA_3R_0D:
     case OPC_MSA_3R_0E:
     case OPC_MSA_3R_0F:
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 15/33] target/mips: Convert MSA load/store instruction format to decodetree
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (13 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 14/33] target/mips: Convert MSA I8 instruction format " Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-24  4:53   ` Richard Henderson
  2021-10-23 21:47 ` [PATCH 16/33] target/mips: Convert MSA 2RF " Philippe Mathieu-Daudé
                   ` (18 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Convert load/store instructions to decodetree.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      |  4 ++
 target/mips/tcg/msa_translate.c | 99 +++++++++++++--------------------
 2 files changed, 44 insertions(+), 59 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 3dd07dced57..5fe6923ace5 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -17,6 +17,7 @@
 &msa_ldst           df wd ws    sa
 
 @lsa                ...... rs:5 rt:5 rd:5 ... sa:2 ......   &r
+@ldst               ...... sa:s10 ws:5 wd:5 .... df:2       &msa_ldst
 @bz_v               ...... ... ..    wt:5 sa:16             &msa_bz df=3
 @bz                 ...... ...  df:2 wt:5 sa:16             &msa_bz
 @u5                 ...... ... df:2 sa:5  ws:5 wd:5 ......  &msa_ldst
@@ -73,5 +74,8 @@ BNZ                 010001 111 .. ..... ................    @bz
   SRARI             011110 010 ....... ..... .....  001010  @bit
   SRLRI             011110 011 ....... ..... .....  001010  @bit
 
+  LD                011110 .......... ..... .....   1000 .. @ldst
+  ST                011110 .......... ..... .....   1001 .. @ldst
+
   MSA               011110 --------------------------
 }
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 2866687635d..52af99636a4 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -38,16 +38,6 @@ enum {
     OPC_MSA_3RF_1B  = 0x1B | OPC_MSA,
     OPC_MSA_3RF_1C  = 0x1C | OPC_MSA,
     OPC_MSA_VEC     = 0x1E | OPC_MSA,
-
-    /* MI10 instruction */
-    OPC_LD_B        = (0x20) | OPC_MSA,
-    OPC_LD_H        = (0x21) | OPC_MSA,
-    OPC_LD_W        = (0x22) | OPC_MSA,
-    OPC_LD_D        = (0x23) | OPC_MSA,
-    OPC_ST_B        = (0x24) | OPC_MSA,
-    OPC_ST_H        = (0x25) | OPC_MSA,
-    OPC_ST_W        = (0x26) | OPC_MSA,
-    OPC_ST_D        = (0x27) | OPC_MSA,
 };
 
 enum {
@@ -298,6 +288,10 @@ static inline bool check_msa_access(DisasContext *ctx)
 #define TRANS_MSA(NAME, trans_func, gen_func) \
         TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, gen_func)
 
+#define TRANS_DF_E(NAME, trans_func, gen_func) \
+        TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
+                    gen_func##_b, gen_func##_h, gen_func##_w, gen_func##_d)
+
 static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
                                    TCGCond cond)
 {
@@ -2104,55 +2098,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
     case OPC_MSA_VEC:
         gen_msa_vec(ctx);
         break;
-    case OPC_LD_B:
-    case OPC_LD_H:
-    case OPC_LD_W:
-    case OPC_LD_D:
-    case OPC_ST_B:
-    case OPC_ST_H:
-    case OPC_ST_W:
-    case OPC_ST_D:
-        {
-            int32_t s10 = sextract32(ctx->opcode, 16, 10);
-            uint8_t rs = (ctx->opcode >> 11) & 0x1f;
-            uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-            uint8_t df = (ctx->opcode >> 0) & 0x3;
-
-            TCGv_i32 twd = tcg_const_i32(wd);
-            TCGv taddr = tcg_temp_new();
-            gen_base_offset_addr(ctx, taddr, rs, s10 << df);
-
-            switch (MASK_MSA_MINOR(opcode)) {
-            case OPC_LD_B:
-                gen_helper_msa_ld_b(cpu_env, twd, taddr);
-                break;
-            case OPC_LD_H:
-                gen_helper_msa_ld_h(cpu_env, twd, taddr);
-                break;
-            case OPC_LD_W:
-                gen_helper_msa_ld_w(cpu_env, twd, taddr);
-                break;
-            case OPC_LD_D:
-                gen_helper_msa_ld_d(cpu_env, twd, taddr);
-                break;
-            case OPC_ST_B:
-                gen_helper_msa_st_b(cpu_env, twd, taddr);
-                break;
-            case OPC_ST_H:
-                gen_helper_msa_st_h(cpu_env, twd, taddr);
-                break;
-            case OPC_ST_W:
-                gen_helper_msa_st_w(cpu_env, twd, taddr);
-                break;
-            case OPC_ST_D:
-                gen_helper_msa_st_d(cpu_env, twd, taddr);
-                break;
-            }
-
-            tcg_temp_free_i32(twd);
-            tcg_temp_free(taddr);
-        }
-        break;
     default:
         MIPS_INVAL("MSA instruction");
         gen_reserved_instruction(ctx);
@@ -2162,6 +2107,42 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
     return true;
 }
 
+static bool trans_msa_ldst(DisasContext *ctx, arg_msa_ldst *a,
+                           void (*gen_msa_b)(TCGv_ptr, TCGv_i32, TCGv),
+                           void (*gen_msa_h)(TCGv_ptr, TCGv_i32, TCGv),
+                           void (*gen_msa_w)(TCGv_ptr, TCGv_i32, TCGv),
+                           void (*gen_msa_d)(TCGv_ptr, TCGv_i32, TCGv))
+{
+
+    TCGv_i32 twd = tcg_const_i32(a->wd);
+    TCGv taddr = tcg_temp_new();
+
+    gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df);
+
+    switch (a->df) {
+    case DF_BYTE:
+        gen_msa_b(cpu_env, twd, taddr);
+        break;
+    case DF_HALF:
+        gen_msa_h(cpu_env, twd, taddr);
+        break;
+    case DF_WORD:
+        gen_msa_w(cpu_env, twd, taddr);
+        break;
+    case DF_DOUBLE:
+        gen_msa_d(cpu_env, twd, taddr);
+        break;
+    }
+
+    tcg_temp_free_i32(twd);
+    tcg_temp_free(taddr);
+
+    return true;
+}
+
+TRANS_DF_E(LD, trans_msa_ldst, gen_helper_msa_ld);
+TRANS_DF_E(ST, trans_msa_ldst, gen_helper_msa_st);
+
 static bool trans_LSA(DisasContext *ctx, arg_r *a)
 {
     return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 16/33] target/mips: Convert MSA 2RF instruction format to decodetree
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (14 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 15/33] target/mips: Convert MSA load/store " Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-24  5:01   ` Richard Henderson
  2021-10-23 21:47 ` [PATCH 17/33] target/mips: Convert MSA FILL opcode " Philippe Mathieu-Daudé
                   ` (17 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Convert 2-register floating-point operations to decodetree.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      |  19 ++++++
 target/mips/tcg/msa_translate.c | 109 ++++++++------------------------
 2 files changed, 46 insertions(+), 82 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 5fe6923ace5..2997bfa24e3 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -13,6 +13,7 @@
 
 &r                  rs rt rd sa
 
+&msa_r              df wd ws wt
 &msa_bz             df       wt sa
 &msa_ldst           df wd ws    sa
 
@@ -20,6 +21,7 @@
 @ldst               ...... sa:s10 ws:5 wd:5 .... df:2       &msa_ldst
 @bz_v               ...... ... ..    wt:5 sa:16             &msa_bz df=3
 @bz                 ...... ...  df:2 wt:5 sa:16             &msa_bz
+@2rf                ...... ......... df:1 ws:5 wd:5 ......  &msa_r wt=0
 @u5                 ...... ... df:2 sa:5  ws:5 wd:5 ......  &msa_ldst
 @s5                 ...... ... df:2 sa:s5 ws:5 wd:5 ......  &msa_ldst
 @ldi                ...... ... df:2 sa:s10     wd:5 ......  &msa_ldst ws=0
@@ -74,6 +76,23 @@ BNZ                 010001 111 .. ..... ................    @bz
   SRARI             011110 010 ....... ..... .....  001010  @bit
   SRLRI             011110 011 ....... ..... .....  001010  @bit
 
+  FCLASS            011110 110010000 . ..... .....  011110  @2rf
+  FTRUNC_S          011110 110010001 . ..... .....  011110  @2rf
+  FTRUNC_U          011110 110010010 . ..... .....  011110  @2rf
+  FSQRT             011110 110010011 . ..... .....  011110  @2rf
+  FRSQRT            011110 110010100 . ..... .....  011110  @2rf
+  FRCP              011110 110010101 . ..... .....  011110  @2rf
+  FRINT             011110 110010110 . ..... .....  011110  @2rf
+  FLOG2             011110 110010111 . ..... .....  011110  @2rf
+  FEXUPL            011110 110011000 . ..... .....  011110  @2rf
+  FEXUPR            011110 110011001 . ..... .....  011110  @2rf
+  FFQL              011110 110011010 . ..... .....  011110  @2rf
+  FFQR              011110 110011011 . ..... .....  011110  @2rf
+  FTINT_S           011110 110011100 . ..... .....  011110  @2rf
+  FTINT_U           011110 110011101 . ..... .....  011110  @2rf
+  FFINT_S           011110 110011110 . ..... .....  011110  @2rf
+  FFINT_U           011110 110011111 . ..... .....  011110  @2rf
+
   LD                011110 .......... ..... .....   1000 .. @ldst
   ST                011110 .......... ..... .....   1001 .. @ldst
 
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 52af99636a4..c6a77381c0e 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -41,7 +41,7 @@ enum {
 };
 
 enum {
-    /* VEC/2R/2RF instruction */
+    /* VEC/2R instruction */
     OPC_AND_V       = (0x00 << 21) | OPC_MSA_VEC,
     OPC_OR_V        = (0x01 << 21) | OPC_MSA_VEC,
     OPC_NOR_V       = (0x02 << 21) | OPC_MSA_VEC,
@@ -51,7 +51,6 @@ enum {
     OPC_BSEL_V      = (0x06 << 21) | OPC_MSA_VEC,
 
     OPC_MSA_2R      = (0x18 << 21) | OPC_MSA_VEC,
-    OPC_MSA_2RF     = (0x19 << 21) | OPC_MSA_VEC,
 
     /* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
     OPC_FILL_df     = (0x00 << 18) | OPC_MSA_2R,
@@ -59,24 +58,6 @@ enum {
     OPC_NLOC_df     = (0x02 << 18) | OPC_MSA_2R,
     OPC_NLZC_df     = (0x03 << 18) | OPC_MSA_2R,
 
-    /* 2RF instruction df(bit 16) = _w, _d */
-    OPC_FCLASS_df   = (0x00 << 17) | OPC_MSA_2RF,
-    OPC_FTRUNC_S_df = (0x01 << 17) | OPC_MSA_2RF,
-    OPC_FTRUNC_U_df = (0x02 << 17) | OPC_MSA_2RF,
-    OPC_FSQRT_df    = (0x03 << 17) | OPC_MSA_2RF,
-    OPC_FRSQRT_df   = (0x04 << 17) | OPC_MSA_2RF,
-    OPC_FRCP_df     = (0x05 << 17) | OPC_MSA_2RF,
-    OPC_FRINT_df    = (0x06 << 17) | OPC_MSA_2RF,
-    OPC_FLOG2_df    = (0x07 << 17) | OPC_MSA_2RF,
-    OPC_FEXUPL_df   = (0x08 << 17) | OPC_MSA_2RF,
-    OPC_FEXUPR_df   = (0x09 << 17) | OPC_MSA_2RF,
-    OPC_FFQL_df     = (0x0A << 17) | OPC_MSA_2RF,
-    OPC_FFQR_df     = (0x0B << 17) | OPC_MSA_2RF,
-    OPC_FTINT_S_df  = (0x0C << 17) | OPC_MSA_2RF,
-    OPC_FTINT_U_df  = (0x0D << 17) | OPC_MSA_2RF,
-    OPC_FFINT_S_df  = (0x0E << 17) | OPC_MSA_2RF,
-    OPC_FFINT_U_df  = (0x0F << 17) | OPC_MSA_2RF,
-
     /* 3R instruction df(bits 22..21) = _b, _h, _w, d */
     OPC_SLL_df      = (0x0 << 23) | OPC_MSA_3R_0D,
     OPC_ADDV_df     = (0x0 << 23) | OPC_MSA_3R_0E,
@@ -1932,73 +1913,40 @@ static void gen_msa_2r(DisasContext *ctx)
     tcg_temp_free_i32(tws);
 }
 
-static void gen_msa_2rf(DisasContext *ctx)
+static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a,
+                          void (*gen_msa_2rf)(TCGv_ptr, TCGv_i32,
+                                              TCGv_i32, TCGv_i32))
 {
-#define MASK_MSA_2RF(op)    (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
-                            (op & (0xf << 17)))
-    uint8_t ws = (ctx->opcode >> 11) & 0x1f;
-    uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-    uint8_t df = (ctx->opcode >> 16) & 0x1;
-    TCGv_i32 twd = tcg_const_i32(wd);
-    TCGv_i32 tws = tcg_const_i32(ws);
+    TCGv_i32 twd = tcg_const_i32(a->wd);
+    TCGv_i32 tws = tcg_const_i32(a->ws);
     /* adjust df value for floating-point instruction */
-    TCGv_i32 tdf = tcg_constant_i32(DF_WORD + df);
+    TCGv_i32 tdf = tcg_constant_i32(DF_WORD + a->df);
 
-    switch (MASK_MSA_2RF(ctx->opcode)) {
-    case OPC_FCLASS_df:
-        gen_helper_msa_fclass_df(cpu_env, tdf, twd, tws);
-        break;
-    case OPC_FTRUNC_S_df:
-        gen_helper_msa_ftrunc_s_df(cpu_env, tdf, twd, tws);
-        break;
-    case OPC_FTRUNC_U_df:
-        gen_helper_msa_ftrunc_u_df(cpu_env, tdf, twd, tws);
-        break;
-    case OPC_FSQRT_df:
-        gen_helper_msa_fsqrt_df(cpu_env, tdf, twd, tws);
-        break;
-    case OPC_FRSQRT_df:
-        gen_helper_msa_frsqrt_df(cpu_env, tdf, twd, tws);
-        break;
-    case OPC_FRCP_df:
-        gen_helper_msa_frcp_df(cpu_env, tdf, twd, tws);
-        break;
-    case OPC_FRINT_df:
-        gen_helper_msa_frint_df(cpu_env, tdf, twd, tws);
-        break;
-    case OPC_FLOG2_df:
-        gen_helper_msa_flog2_df(cpu_env, tdf, twd, tws);
-        break;
-    case OPC_FEXUPL_df:
-        gen_helper_msa_fexupl_df(cpu_env, tdf, twd, tws);
-        break;
-    case OPC_FEXUPR_df:
-        gen_helper_msa_fexupr_df(cpu_env, tdf, twd, tws);
-        break;
-    case OPC_FFQL_df:
-        gen_helper_msa_ffql_df(cpu_env, tdf, twd, tws);
-        break;
-    case OPC_FFQR_df:
-        gen_helper_msa_ffqr_df(cpu_env, tdf, twd, tws);
-        break;
-    case OPC_FTINT_S_df:
-        gen_helper_msa_ftint_s_df(cpu_env, tdf, twd, tws);
-        break;
-    case OPC_FTINT_U_df:
-        gen_helper_msa_ftint_u_df(cpu_env, tdf, twd, tws);
-        break;
-    case OPC_FFINT_S_df:
-        gen_helper_msa_ffint_s_df(cpu_env, tdf, twd, tws);
-        break;
-    case OPC_FFINT_U_df:
-        gen_helper_msa_ffint_u_df(cpu_env, tdf, twd, tws);
-        break;
-    }
+    gen_msa_2rf(cpu_env, tdf, twd, tws);
 
     tcg_temp_free_i32(twd);
     tcg_temp_free_i32(tws);
+
+    return true;
 }
 
+TRANS_MSA(FCLASS,   trans_msa_2rf, gen_helper_msa_fclass_df);
+TRANS_MSA(FTRUNC_S, trans_msa_2rf, gen_helper_msa_fclass_df);
+TRANS_MSA(FTRUNC_U, trans_msa_2rf, gen_helper_msa_ftrunc_s_df);
+TRANS_MSA(FSQRT,    trans_msa_2rf, gen_helper_msa_fsqrt_df);
+TRANS_MSA(FRSQRT,   trans_msa_2rf, gen_helper_msa_frsqrt_df);
+TRANS_MSA(FRCP,     trans_msa_2rf, gen_helper_msa_frcp_df);
+TRANS_MSA(FRINT,    trans_msa_2rf, gen_helper_msa_frint_df);
+TRANS_MSA(FLOG2,    trans_msa_2rf, gen_helper_msa_flog2_df);
+TRANS_MSA(FEXUPL,   trans_msa_2rf, gen_helper_msa_fexupl_df);
+TRANS_MSA(FEXUPR,   trans_msa_2rf, gen_helper_msa_fexupr_df);
+TRANS_MSA(FFQL,     trans_msa_2rf, gen_helper_msa_ffql_df);
+TRANS_MSA(FFQR,     trans_msa_2rf, gen_helper_msa_ffqr_df);
+TRANS_MSA(FTINT_S,  trans_msa_2rf, gen_helper_msa_ftint_s_df);
+TRANS_MSA(FTINT_U,  trans_msa_2rf, gen_helper_msa_ftint_u_df);
+TRANS_MSA(FFINT_S,  trans_msa_2rf, gen_helper_msa_ffint_s_df);
+TRANS_MSA(FFINT_U,  trans_msa_2rf, gen_helper_msa_ffint_u_df);
+
 static void gen_msa_vec_v(DisasContext *ctx)
 {
 #define MASK_MSA_VEC(op)    (MASK_MSA_MINOR(op) | (op & (0x1f << 21)))
@@ -2057,9 +2005,6 @@ static void gen_msa_vec(DisasContext *ctx)
     case OPC_MSA_2R:
         gen_msa_2r(ctx);
         break;
-    case OPC_MSA_2RF:
-        gen_msa_2rf(ctx);
-        break;
     default:
         MIPS_INVAL("MSA instruction");
         gen_reserved_instruction(ctx);
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 17/33] target/mips: Convert MSA FILL opcode to decodetree
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (15 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 16/33] target/mips: Convert MSA 2RF " Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-24  5:04   ` Richard Henderson
  2021-10-23 21:47 ` [PATCH 18/33] target/mips: Convert MSA 2R instruction format " Philippe Mathieu-Daudé
                   ` (16 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Convert the FILL opcode (Vector Fill from GPR) to decodetree.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      |  2 ++
 target/mips/tcg/msa_translate.c | 40 +++++++++++++++++++++++----------
 2 files changed, 30 insertions(+), 12 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 2997bfa24e3..e97490cf880 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -21,6 +21,7 @@
 @ldst               ...... sa:s10 ws:5 wd:5 .... df:2       &msa_ldst
 @bz_v               ...... ... ..    wt:5 sa:16             &msa_bz df=3
 @bz                 ...... ...  df:2 wt:5 sa:16             &msa_bz
+@2r                 ...... ........  df:2 ws:5 wd:5 ......  &msa_r wt=0
 @2rf                ...... ......... df:1 ws:5 wd:5 ......  &msa_r wt=0
 @u5                 ...... ... df:2 sa:5  ws:5 wd:5 ......  &msa_ldst
 @s5                 ...... ... df:2 sa:s5 ws:5 wd:5 ......  &msa_ldst
@@ -76,6 +77,7 @@ BNZ                 010001 111 .. ..... ................    @bz
   SRARI             011110 010 ....... ..... .....  001010  @bit
   SRLRI             011110 011 ....... ..... .....  001010  @bit
 
+  FILL              011110 11000000 .. ..... .....  011110  @2r
   FCLASS            011110 110010000 . ..... .....  011110  @2rf
   FTRUNC_S          011110 110010001 . ..... .....  011110  @2rf
   FTRUNC_U          011110 110010010 . ..... .....  011110  @2rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index c6a77381c0e..fc0b80f83ac 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -53,7 +53,6 @@ enum {
     OPC_MSA_2R      = (0x18 << 21) | OPC_MSA_VEC,
 
     /* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
-    OPC_FILL_df     = (0x00 << 18) | OPC_MSA_2R,
     OPC_PCNT_df     = (0x01 << 18) | OPC_MSA_2R,
     OPC_NLOC_df     = (0x02 << 18) | OPC_MSA_2R,
     OPC_NLZC_df     = (0x03 << 18) | OPC_MSA_2R,
@@ -1844,17 +1843,6 @@ static void gen_msa_2r(DisasContext *ctx)
     TCGv_i32 tws = tcg_const_i32(ws);
 
     switch (MASK_MSA_2R(ctx->opcode)) {
-    case OPC_FILL_df:
-#if !defined(TARGET_MIPS64)
-        /* Double format valid only for MIPS64 */
-        if (df == DF_DOUBLE) {
-            gen_reserved_instruction(ctx);
-            break;
-        }
-#endif
-        gen_helper_msa_fill_df(cpu_env, tcg_constant_i32(df),
-                               twd, tws); /* trs */
-        break;
     case OPC_NLOC_df:
         switch (df) {
         case DF_BYTE:
@@ -1913,6 +1901,34 @@ static void gen_msa_2r(DisasContext *ctx)
     tcg_temp_free_i32(tws);
 }
 
+static bool trans_FILL(DisasContext *ctx, arg_msa_r *a)
+{
+    TCGv_i32 twd;
+    TCGv_i32 tws;
+    TCGv_i32 tdf;
+
+    if (!check_msa_access(ctx)) {
+        return false;
+    }
+
+    if (TARGET_LONG_BITS != 64 && a->df == DF_DOUBLE) {
+        /* Double format valid only for MIPS64 */
+        gen_reserved_instruction(ctx);
+        return true;
+    }
+
+    twd = tcg_const_i32(a->wd);
+    tws = tcg_const_i32(a->ws);
+    tdf = tcg_constant_i32(a->df);
+
+    gen_helper_msa_fill_df(cpu_env, tdf, twd, tws); /* trs */
+
+    tcg_temp_free_i32(twd);
+    tcg_temp_free_i32(tws);
+
+    return true;
+}
+
 static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a,
                           void (*gen_msa_2rf)(TCGv_ptr, TCGv_i32,
                                               TCGv_i32, TCGv_i32))
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 18/33] target/mips: Convert MSA 2R instruction format to decodetree
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (16 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 17/33] target/mips: Convert MSA FILL opcode " Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-24  5:14   ` Richard Henderson
  2021-10-23 21:47 ` [PATCH 19/33] target/mips: Convert MSA VEC " Philippe Mathieu-Daudé
                   ` (15 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Convert 2-register operations to decodetree.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      |  3 ++
 target/mips/tcg/msa_translate.c | 91 +++++++++------------------------
 2 files changed, 28 insertions(+), 66 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index e97490cf880..88757f547eb 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -78,6 +78,9 @@ BNZ                 010001 111 .. ..... ................    @bz
   SRLRI             011110 011 ....... ..... .....  001010  @bit
 
   FILL              011110 11000000 .. ..... .....  011110  @2r
+  PCNT              011110 11000001 .. ..... .....  011110  @2r
+  NLOC              011110 11000010 .. ..... .....  011110  @2r
+  NLZC              011110 11000011 .. ..... .....  011110  @2r
   FCLASS            011110 110010000 . ..... .....  011110  @2rf
   FTRUNC_S          011110 110010001 . ..... .....  011110  @2rf
   FTRUNC_U          011110 110010010 . ..... .....  011110  @2rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index fc0b80f83ac..f54e9d173ac 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -50,13 +50,6 @@ enum {
     OPC_BMZ_V       = (0x05 << 21) | OPC_MSA_VEC,
     OPC_BSEL_V      = (0x06 << 21) | OPC_MSA_VEC,
 
-    OPC_MSA_2R      = (0x18 << 21) | OPC_MSA_VEC,
-
-    /* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
-    OPC_PCNT_df     = (0x01 << 18) | OPC_MSA_2R,
-    OPC_NLOC_df     = (0x02 << 18) | OPC_MSA_2R,
-    OPC_NLZC_df     = (0x03 << 18) | OPC_MSA_2R,
-
     /* 3R instruction df(bits 22..21) = _b, _h, _w, d */
     OPC_SLL_df      = (0x0 << 23) | OPC_MSA_3R_0D,
     OPC_ADDV_df     = (0x0 << 23) | OPC_MSA_3R_0E,
@@ -1832,75 +1825,44 @@ static void gen_msa_3rf(DisasContext *ctx)
     tcg_temp_free_i32(twt);
 }
 
-static void gen_msa_2r(DisasContext *ctx)
+static bool trans_msa_2r(DisasContext *ctx, arg_msa_r *a,
+                         void (*gen_msa_2r_b)(TCGv_ptr, TCGv_i32, TCGv_i32),
+                         void (*gen_msa_2r_h)(TCGv_ptr, TCGv_i32, TCGv_i32),
+                         void (*gen_msa_2r_w)(TCGv_ptr, TCGv_i32, TCGv_i32),
+                         void (*gen_msa_2r_d)(TCGv_ptr, TCGv_i32, TCGv_i32))
 {
-#define MASK_MSA_2R(op)     (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
-                            (op & (0x7 << 18)))
-    uint8_t ws = (ctx->opcode >> 11) & 0x1f;
-    uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-    uint8_t df = (ctx->opcode >> 16) & 0x3;
-    TCGv_i32 twd = tcg_const_i32(wd);
-    TCGv_i32 tws = tcg_const_i32(ws);
+    TCGv_i32 twd = tcg_const_i32(a->wd);
+    TCGv_i32 tws = tcg_const_i32(a->ws);
 
-    switch (MASK_MSA_2R(ctx->opcode)) {
-    case OPC_NLOC_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_nloc_b(cpu_env, twd, tws);
-            break;
-        case DF_HALF:
-            gen_helper_msa_nloc_h(cpu_env, twd, tws);
-            break;
-        case DF_WORD:
-            gen_helper_msa_nloc_w(cpu_env, twd, tws);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_nloc_d(cpu_env, twd, tws);
-            break;
+    switch (a->df) {
+    case DF_BYTE:
+        if (gen_msa_2r_b == NULL) {
+            gen_reserved_instruction(ctx);
+        } else {
+            gen_msa_2r_b(cpu_env, twd, tws);
         }
         break;
-    case OPC_NLZC_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_nlzc_b(cpu_env, twd, tws);
-            break;
-        case DF_HALF:
-            gen_helper_msa_nlzc_h(cpu_env, twd, tws);
-            break;
-        case DF_WORD:
-            gen_helper_msa_nlzc_w(cpu_env, twd, tws);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_nlzc_d(cpu_env, twd, tws);
-            break;
-        }
+    case DF_HALF:
+        gen_msa_2r_h(cpu_env, twd, tws);
         break;
-    case OPC_PCNT_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_pcnt_b(cpu_env, twd, tws);
-            break;
-        case DF_HALF:
-            gen_helper_msa_pcnt_h(cpu_env, twd, tws);
-            break;
-        case DF_WORD:
-            gen_helper_msa_pcnt_w(cpu_env, twd, tws);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_pcnt_d(cpu_env, twd, tws);
-            break;
-        }
+    case DF_WORD:
+        gen_msa_2r_w(cpu_env, twd, tws);
         break;
-    default:
-        MIPS_INVAL("MSA instruction");
-        gen_reserved_instruction(ctx);
+    case DF_DOUBLE:
+        gen_msa_2r_d(cpu_env, twd, tws);
         break;
     }
 
     tcg_temp_free_i32(twd);
     tcg_temp_free_i32(tws);
+
+    return true;
 }
 
+TRANS_DF_E(PCNT, trans_msa_2r, gen_helper_msa_pcnt);
+TRANS_DF_E(NLOC, trans_msa_2r, gen_helper_msa_nloc);
+TRANS_DF_E(NLZC, trans_msa_2r, gen_helper_msa_nlzc);
+
 static bool trans_FILL(DisasContext *ctx, arg_msa_r *a)
 {
     TCGv_i32 twd;
@@ -2018,9 +1980,6 @@ static void gen_msa_vec(DisasContext *ctx)
     case OPC_BSEL_V:
         gen_msa_vec_v(ctx);
         break;
-    case OPC_MSA_2R:
-        gen_msa_2r(ctx);
-        break;
     default:
         MIPS_INVAL("MSA instruction");
         gen_reserved_instruction(ctx);
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 19/33] target/mips: Convert MSA VEC instruction format to decodetree
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (17 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 18/33] target/mips: Convert MSA 2R instruction format " Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-24  5:17   ` Richard Henderson
  2021-10-23 21:47 ` [PATCH 20/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Philippe Mathieu-Daudé
                   ` (14 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Convert 3-register instructions with implicit data formats
to decodetree.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      |  8 ++++
 target/mips/tcg/msa_translate.c | 82 +++++++--------------------------
 2 files changed, 24 insertions(+), 66 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 88757f547eb..72447041fef 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -21,6 +21,7 @@
 @ldst               ...... sa:s10 ws:5 wd:5 .... df:2       &msa_ldst
 @bz_v               ...... ... ..    wt:5 sa:16             &msa_bz df=3
 @bz                 ...... ...  df:2 wt:5 sa:16             &msa_bz
+@vec                ...... .....     wt:5 ws:5 wd:5 ......  &msa_r df=0
 @2r                 ...... ........  df:2 ws:5 wd:5 ......  &msa_r wt=0
 @2rf                ...... ......... df:1 ws:5 wd:5 ......  &msa_r wt=0
 @u5                 ...... ... df:2 sa:5  ws:5 wd:5 ......  &msa_ldst
@@ -77,6 +78,13 @@ BNZ                 010001 111 .. ..... ................    @bz
   SRARI             011110 010 ....... ..... .....  001010  @bit
   SRLRI             011110 011 ....... ..... .....  001010  @bit
 
+  AND_V             011110 00000 ..... ..... .....  011110  @vec
+  OR_V              011110 00001 ..... ..... .....  011110  @vec
+  NOR_V             011110 00010 ..... ..... .....  011110  @vec
+  XOR_V             011110 00011 ..... ..... .....  011110  @vec
+  BMNZ_V            011110 00100 ..... ..... .....  011110  @vec
+  BMZ_V             011110 00101 ..... ..... .....  011110  @vec
+  BSEL_V            011110 00110 ..... ..... .....  011110  @vec
   FILL              011110 11000000 .. ..... .....  011110  @2r
   PCNT              011110 11000001 .. ..... .....  011110  @2r
   NLOC              011110 11000010 .. ..... .....  011110  @2r
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index f54e9d173ac..461a427c9df 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -37,19 +37,9 @@ enum {
     OPC_MSA_3RF_1A  = 0x1A | OPC_MSA,
     OPC_MSA_3RF_1B  = 0x1B | OPC_MSA,
     OPC_MSA_3RF_1C  = 0x1C | OPC_MSA,
-    OPC_MSA_VEC     = 0x1E | OPC_MSA,
 };
 
 enum {
-    /* VEC/2R instruction */
-    OPC_AND_V       = (0x00 << 21) | OPC_MSA_VEC,
-    OPC_OR_V        = (0x01 << 21) | OPC_MSA_VEC,
-    OPC_NOR_V       = (0x02 << 21) | OPC_MSA_VEC,
-    OPC_XOR_V       = (0x03 << 21) | OPC_MSA_VEC,
-    OPC_BMNZ_V      = (0x04 << 21) | OPC_MSA_VEC,
-    OPC_BMZ_V       = (0x05 << 21) | OPC_MSA_VEC,
-    OPC_BSEL_V      = (0x06 << 21) | OPC_MSA_VEC,
-
     /* 3R instruction df(bits 22..21) = _b, _h, _w, d */
     OPC_SLL_df      = (0x0 << 23) | OPC_MSA_3R_0D,
     OPC_ADDV_df     = (0x0 << 23) | OPC_MSA_3R_0E,
@@ -1925,67 +1915,30 @@ TRANS_MSA(FTINT_U,  trans_msa_2rf, gen_helper_msa_ftint_u_df);
 TRANS_MSA(FFINT_S,  trans_msa_2rf, gen_helper_msa_ffint_s_df);
 TRANS_MSA(FFINT_U,  trans_msa_2rf, gen_helper_msa_ffint_u_df);
 
-static void gen_msa_vec_v(DisasContext *ctx)
+static bool trans_msa_vec(DisasContext *ctx, arg_msa_r *a,
+                          void (*gen_msa_vec)(TCGv_ptr, TCGv_i32,
+                                              TCGv_i32, TCGv_i32))
 {
-#define MASK_MSA_VEC(op)    (MASK_MSA_MINOR(op) | (op & (0x1f << 21)))
-    uint8_t wt = (ctx->opcode >> 16) & 0x1f;
-    uint8_t ws = (ctx->opcode >> 11) & 0x1f;
-    uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-    TCGv_i32 twd = tcg_const_i32(wd);
-    TCGv_i32 tws = tcg_const_i32(ws);
-    TCGv_i32 twt = tcg_const_i32(wt);
+    TCGv_i32 twd = tcg_const_i32(a->wd);
+    TCGv_i32 tws = tcg_const_i32(a->ws);
+    TCGv_i32 twt = tcg_const_i32(a->wt);
 
-    switch (MASK_MSA_VEC(ctx->opcode)) {
-    case OPC_AND_V:
-        gen_helper_msa_and_v(cpu_env, twd, tws, twt);
-        break;
-    case OPC_OR_V:
-        gen_helper_msa_or_v(cpu_env, twd, tws, twt);
-        break;
-    case OPC_NOR_V:
-        gen_helper_msa_nor_v(cpu_env, twd, tws, twt);
-        break;
-    case OPC_XOR_V:
-        gen_helper_msa_xor_v(cpu_env, twd, tws, twt);
-        break;
-    case OPC_BMNZ_V:
-        gen_helper_msa_bmnz_v(cpu_env, twd, tws, twt);
-        break;
-    case OPC_BMZ_V:
-        gen_helper_msa_bmz_v(cpu_env, twd, tws, twt);
-        break;
-    case OPC_BSEL_V:
-        gen_helper_msa_bsel_v(cpu_env, twd, tws, twt);
-        break;
-    default:
-        MIPS_INVAL("MSA instruction");
-        gen_reserved_instruction(ctx);
-        break;
-    }
+    gen_msa_vec(cpu_env, twd, tws, twt);
 
     tcg_temp_free_i32(twd);
     tcg_temp_free_i32(tws);
     tcg_temp_free_i32(twt);
+
+    return true;
 }
 
-static void gen_msa_vec(DisasContext *ctx)
-{
-    switch (MASK_MSA_VEC(ctx->opcode)) {
-    case OPC_AND_V:
-    case OPC_OR_V:
-    case OPC_NOR_V:
-    case OPC_XOR_V:
-    case OPC_BMNZ_V:
-    case OPC_BMZ_V:
-    case OPC_BSEL_V:
-        gen_msa_vec_v(ctx);
-        break;
-    default:
-        MIPS_INVAL("MSA instruction");
-        gen_reserved_instruction(ctx);
-        break;
-    }
-}
+TRANS_MSA(AND_V,    trans_msa_vec, gen_helper_msa_and_v);
+TRANS_MSA(OR_V,     trans_msa_vec, gen_helper_msa_or_v);
+TRANS_MSA(NOR_V,    trans_msa_vec, gen_helper_msa_nor_v);
+TRANS_MSA(XOR_V,    trans_msa_vec, gen_helper_msa_xor_v);
+TRANS_MSA(BMNZ_V,   trans_msa_vec, gen_helper_msa_bmnz_v);
+TRANS_MSA(BMZ_V,    trans_msa_vec, gen_helper_msa_bmz_v);
+TRANS_MSA(BSEL_V,   trans_msa_vec, gen_helper_msa_bsel_v);
 
 static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
 {
@@ -2015,9 +1968,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
     case OPC_MSA_3RF_1C:
         gen_msa_3rf(ctx);
         break;
-    case OPC_MSA_VEC:
-        gen_msa_vec(ctx);
-        break;
     default:
         MIPS_INVAL("MSA instruction");
         gen_reserved_instruction(ctx);
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 20/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (18 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 19/33] target/mips: Convert MSA VEC " Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-24 17:37   ` Richard Henderson
  2021-10-23 21:47 ` [PATCH 21/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) Philippe Mathieu-Daudé
                   ` (13 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Convert 3-register floating-point or fixed-point operations
to decodetree.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      |  8 ++++
 target/mips/tcg/msa_translate.c | 70 +++++++++++++++------------------
 2 files changed, 39 insertions(+), 39 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 72447041fef..5c6a7415271 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -24,6 +24,7 @@
 @vec                ...... .....     wt:5 ws:5 wd:5 ......  &msa_r df=0
 @2r                 ...... ........  df:2 ws:5 wd:5 ......  &msa_r wt=0
 @2rf                ...... ......... df:1 ws:5 wd:5 ......  &msa_r wt=0
+@3rf                ...... .... df:1 wt:5 ws:5 wd:5 ......  &msa_r
 @u5                 ...... ... df:2 sa:5  ws:5 wd:5 ......  &msa_ldst
 @s5                 ...... ... df:2 sa:s5 ws:5 wd:5 ......  &msa_ldst
 @ldi                ...... ... df:2 sa:s10     wd:5 ......  &msa_ldst ws=0
@@ -78,6 +79,13 @@ BNZ                 010001 111 .. ..... ................    @bz
   SRARI             011110 010 ....... ..... .....  001010  @bit
   SRLRI             011110 011 ....... ..... .....  001010  @bit
 
+  MUL_Q             011110 0100 . ..... ..... ..... 011100  @3rf
+  MADD_Q            011110 0101 . ..... ..... ..... 011100  @3rf
+  MSUB_Q            011110 0110 . ..... ..... ..... 011100  @3rf
+  MULR_Q            011110 1100 . ..... ..... ..... 011100  @3rf
+  MADDR_Q           011110 1101 . ..... ..... ..... 011100  @3rf
+  MSUBR_Q           011110 1110 . ..... ..... ..... 011100  @3rf
+
   AND_V             011110 00000 ..... ..... .....  011110  @vec
   OR_V              011110 00001 ..... ..... .....  011110  @vec
   NOR_V             011110 00010 ..... ..... .....  011110  @vec
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 461a427c9df..6e50bc9edf4 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -130,12 +130,9 @@ enum {
     OPC_FCNE_df     = (0x3 << 22) | OPC_MSA_3RF_1C,
     OPC_FCLT_df     = (0x4 << 22) | OPC_MSA_3RF_1A,
     OPC_FMADD_df    = (0x4 << 22) | OPC_MSA_3RF_1B,
-    OPC_MUL_Q_df    = (0x4 << 22) | OPC_MSA_3RF_1C,
     OPC_FCULT_df    = (0x5 << 22) | OPC_MSA_3RF_1A,
     OPC_FMSUB_df    = (0x5 << 22) | OPC_MSA_3RF_1B,
-    OPC_MADD_Q_df   = (0x5 << 22) | OPC_MSA_3RF_1C,
     OPC_FCLE_df     = (0x6 << 22) | OPC_MSA_3RF_1A,
-    OPC_MSUB_Q_df   = (0x6 << 22) | OPC_MSA_3RF_1C,
     OPC_FCULE_df    = (0x7 << 22) | OPC_MSA_3RF_1A,
     OPC_FEXP2_df    = (0x7 << 22) | OPC_MSA_3RF_1B,
     OPC_FSAF_df     = (0x8 << 22) | OPC_MSA_3RF_1A,
@@ -149,13 +146,10 @@ enum {
     OPC_FSNE_df     = (0xB << 22) | OPC_MSA_3RF_1C,
     OPC_FSLT_df     = (0xC << 22) | OPC_MSA_3RF_1A,
     OPC_FMIN_df     = (0xC << 22) | OPC_MSA_3RF_1B,
-    OPC_MULR_Q_df   = (0xC << 22) | OPC_MSA_3RF_1C,
     OPC_FSULT_df    = (0xD << 22) | OPC_MSA_3RF_1A,
     OPC_FMIN_A_df   = (0xD << 22) | OPC_MSA_3RF_1B,
-    OPC_MADDR_Q_df  = (0xD << 22) | OPC_MSA_3RF_1C,
     OPC_FSLE_df     = (0xE << 22) | OPC_MSA_3RF_1A,
     OPC_FMAX_df     = (0xE << 22) | OPC_MSA_3RF_1B,
-    OPC_MSUBR_Q_df  = (0xE << 22) | OPC_MSA_3RF_1C,
     OPC_FSULE_df    = (0xF << 22) | OPC_MSA_3RF_1A,
     OPC_FMAX_A_df   = (0xF << 22) | OPC_MSA_3RF_1B,
 };
@@ -251,6 +245,9 @@ static inline bool check_msa_access(DisasContext *ctx)
 #define TRANS_MSA(NAME, trans_func, gen_func) \
         TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, gen_func)
 
+#define TRANS_DF(NAME, trans_func, df, gen_func) \
+        TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, df, gen_func)
+
 #define TRANS_DF_E(NAME, trans_func, gen_func) \
         TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
                     gen_func##_b, gen_func##_h, gen_func##_w, gen_func##_d)
@@ -1652,6 +1649,33 @@ static void gen_msa_elm(DisasContext *ctx)
     gen_msa_elm_df(ctx, df, n);
 }
 
+static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a,
+                          enum CPUMIPSMSADataFormat df_base,
+                          void (*gen_msa_3rf)(TCGv_ptr, TCGv_i32, TCGv_i32,
+                                              TCGv_i32, TCGv_i32))
+{
+    TCGv_i32 twd = tcg_const_i32(a->wd);
+    TCGv_i32 tws = tcg_const_i32(a->ws);
+    TCGv_i32 twt = tcg_const_i32(a->wt);
+    /* adjust df value for floating-point instruction */
+    TCGv_i32 tdf = tcg_constant_i32(a->df + df_base);
+
+    gen_msa_3rf(cpu_env, tdf, twd, tws, twt);
+
+    tcg_temp_free_i32(twt);
+    tcg_temp_free_i32(tws);
+    tcg_temp_free_i32(twd);
+
+    return true;
+}
+
+TRANS_DF(MUL_Q,     trans_msa_3rf, DF_HALF, gen_helper_msa_mul_q_df);
+TRANS_DF(MADD_Q,    trans_msa_3rf, DF_HALF, gen_helper_msa_madd_q_df);
+TRANS_DF(MSUB_Q,    trans_msa_3rf, DF_HALF, gen_helper_msa_msub_q_df);
+TRANS_DF(MULR_Q,    trans_msa_3rf, DF_HALF, gen_helper_msa_mulr_q_df);
+TRANS_DF(MADDR_Q,   trans_msa_3rf, DF_HALF, gen_helper_msa_maddr_q_df);
+TRANS_DF(MSUBR_Q,   trans_msa_3rf, DF_HALF, gen_helper_msa_msubr_q_df);
+
 static void gen_msa_3rf(DisasContext *ctx)
 {
 #define MASK_MSA_3RF(op)    (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
@@ -1663,22 +1687,8 @@ static void gen_msa_3rf(DisasContext *ctx)
     TCGv_i32 twd = tcg_const_i32(wd);
     TCGv_i32 tws = tcg_const_i32(ws);
     TCGv_i32 twt = tcg_const_i32(wt);
-    TCGv_i32 tdf;
-
     /* adjust df value for floating-point instruction */
-    switch (MASK_MSA_3RF(ctx->opcode)) {
-    case OPC_MUL_Q_df:
-    case OPC_MADD_Q_df:
-    case OPC_MSUB_Q_df:
-    case OPC_MULR_Q_df:
-    case OPC_MADDR_Q_df:
-    case OPC_MSUBR_Q_df:
-        tdf = tcg_constant_i32(DF_HALF + df);
-        break;
-    default:
-        tdf = tcg_constant_i32(DF_WORD + df);
-        break;
-    }
+    TCGv_i32 tdf = tcg_constant_i32(DF_WORD + df);
 
     switch (MASK_MSA_3RF(ctx->opcode)) {
     case OPC_FCAF_df:
@@ -1720,24 +1730,15 @@ static void gen_msa_3rf(DisasContext *ctx)
     case OPC_FMADD_df:
         gen_helper_msa_fmadd_df(cpu_env, tdf, twd, tws, twt);
         break;
-    case OPC_MUL_Q_df:
-        gen_helper_msa_mul_q_df(cpu_env, tdf, twd, tws, twt);
-        break;
     case OPC_FCULT_df:
         gen_helper_msa_fcult_df(cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FMSUB_df:
         gen_helper_msa_fmsub_df(cpu_env, tdf, twd, tws, twt);
         break;
-    case OPC_MADD_Q_df:
-        gen_helper_msa_madd_q_df(cpu_env, tdf, twd, tws, twt);
-        break;
     case OPC_FCLE_df:
         gen_helper_msa_fcle_df(cpu_env, tdf, twd, tws, twt);
         break;
-    case OPC_MSUB_Q_df:
-        gen_helper_msa_msub_q_df(cpu_env, tdf, twd, tws, twt);
-        break;
     case OPC_FCULE_df:
         gen_helper_msa_fcule_df(cpu_env, tdf, twd, tws, twt);
         break;
@@ -1777,27 +1778,18 @@ static void gen_msa_3rf(DisasContext *ctx)
     case OPC_FMIN_df:
         gen_helper_msa_fmin_df(cpu_env, tdf, twd, tws, twt);
         break;
-    case OPC_MULR_Q_df:
-        gen_helper_msa_mulr_q_df(cpu_env, tdf, twd, tws, twt);
-        break;
     case OPC_FSULT_df:
         gen_helper_msa_fsult_df(cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FMIN_A_df:
         gen_helper_msa_fmin_a_df(cpu_env, tdf, twd, tws, twt);
         break;
-    case OPC_MADDR_Q_df:
-        gen_helper_msa_maddr_q_df(cpu_env, tdf, twd, tws, twt);
-        break;
     case OPC_FSLE_df:
         gen_helper_msa_fsle_df(cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FMAX_df:
         gen_helper_msa_fmax_df(cpu_env, tdf, twd, tws, twt);
         break;
-    case OPC_MSUBR_Q_df:
-        gen_helper_msa_msubr_q_df(cpu_env, tdf, twd, tws, twt);
-        break;
     case OPC_FSULE_df:
         gen_helper_msa_fsule_df(cpu_env, tdf, twd, tws, twt);
         break;
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 21/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (19 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 20/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-24 17:42   ` Richard Henderson
  2021-10-23 21:47 ` [PATCH 22/33] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) Philippe Mathieu-Daudé
                   ` (12 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Convert 3-register floating-point or fixed-point operations
to decodetree.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      |  37 ++++++
 target/mips/tcg/msa_translate.c | 213 ++++++--------------------------
 2 files changed, 74 insertions(+), 176 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 5c6a7415271..28b7a71d930 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -79,9 +79,46 @@ BNZ                 010001 111 .. ..... ................    @bz
   SRARI             011110 010 ....... ..... .....  001010  @bit
   SRLRI             011110 011 ....... ..... .....  001010  @bit
 
+  FCAF              011110 0000 . ..... ..... ..... 011010  @3rf
+  FCUN              011110 0001 . ..... ..... ..... 011010  @3rf
+  FCEQ              011110 0010 . ..... ..... ..... 011010  @3rf
+  FCUEQ             011110 0011 . ..... ..... ..... 011010  @3rf
+  FCLT              011110 0100 . ..... ..... ..... 011010  @3rf
+  FCULT             011110 0101 . ..... ..... ..... 011010  @3rf
+  FCLE              011110 0110 . ..... ..... ..... 011010  @3rf
+  FCULE             011110 0111 . ..... ..... ..... 011010  @3rf
+  FSAF              011110 1000 . ..... ..... ..... 011010  @3rf
+  FSUN              011110 1001 . ..... ..... ..... 011010  @3rf
+  FSEQ              011110 1010 . ..... ..... ..... 011010  @3rf
+  FSUEQ             011110 1011 . ..... ..... ..... 011010  @3rf
+  FSLT              011110 1100 . ..... ..... ..... 011010  @3rf
+  FSULT             011110 1101 . ..... ..... ..... 011010  @3rf
+  FSLE              011110 1110 . ..... ..... ..... 011010  @3rf
+  FSULE             011110 1111 . ..... ..... ..... 011010  @3rf
+
+  FADD              011110 0000 . ..... ..... ..... 011011  @3rf
+  FSUB              011110 0001 . ..... ..... ..... 011011  @3rf
+  FMUL              011110 0010 . ..... ..... ..... 011011  @3rf
+  FDIV              011110 0011 . ..... ..... ..... 011011  @3rf
+  FMADD             011110 0100 . ..... ..... ..... 011011  @3rf
+  FMSUB             011110 0101 . ..... ..... ..... 011011  @3rf
+  FEXP2             011110 0111 . ..... ..... ..... 011011  @3rf
+  FEXDO             011110 1000 . ..... ..... ..... 011011  @3rf
+  FTQ               011110 1010 . ..... ..... ..... 011011  @3rf
+  FMIN              011110 1100 . ..... ..... ..... 011011  @3rf
+  FMIN_A            011110 1101 . ..... ..... ..... 011011  @3rf
+  FMAX              011110 1110 . ..... ..... ..... 011011  @3rf
+  FMAX_A            011110 1111 . ..... ..... ..... 011011  @3rf
+
+  FCOR              011110 0001 . ..... ..... ..... 011100  @3rf
+  FCUNE             011110 0010 . ..... ..... ..... 011100  @3rf
+  FCNE              011110 0011 . ..... ..... ..... 011100  @3rf
   MUL_Q             011110 0100 . ..... ..... ..... 011100  @3rf
   MADD_Q            011110 0101 . ..... ..... ..... 011100  @3rf
   MSUB_Q            011110 0110 . ..... ..... ..... 011100  @3rf
+  FSOR              011110 1001 . ..... ..... ..... 011100  @3rf
+  FSUNE             011110 1010 . ..... ..... ..... 011100  @3rf
+  FSNE              011110 1011 . ..... ..... ..... 011100  @3rf
   MULR_Q            011110 1100 . ..... ..... ..... 011100  @3rf
   MADDR_Q           011110 1101 . ..... ..... ..... 011100  @3rf
   MSUBR_Q           011110 1110 . ..... ..... ..... 011100  @3rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 6e50bc9edf4..4543b7abdfb 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -34,9 +34,6 @@ enum {
     OPC_MSA_3R_14   = 0x14 | OPC_MSA,
     OPC_MSA_3R_15   = 0x15 | OPC_MSA,
     OPC_MSA_ELM     = 0x19 | OPC_MSA,
-    OPC_MSA_3RF_1A  = 0x1A | OPC_MSA,
-    OPC_MSA_3RF_1B  = 0x1B | OPC_MSA,
-    OPC_MSA_3RF_1C  = 0x1C | OPC_MSA,
 };
 
 enum {
@@ -115,43 +112,6 @@ enum {
     OPC_COPY_U_df   = (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM,
     OPC_INSERT_df   = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM,
     OPC_INSVE_df    = (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM,
-
-    /* 3RF instruction _df(bit 21) = _w, _d */
-    OPC_FCAF_df     = (0x0 << 22) | OPC_MSA_3RF_1A,
-    OPC_FADD_df     = (0x0 << 22) | OPC_MSA_3RF_1B,
-    OPC_FCUN_df     = (0x1 << 22) | OPC_MSA_3RF_1A,
-    OPC_FSUB_df     = (0x1 << 22) | OPC_MSA_3RF_1B,
-    OPC_FCOR_df     = (0x1 << 22) | OPC_MSA_3RF_1C,
-    OPC_FCEQ_df     = (0x2 << 22) | OPC_MSA_3RF_1A,
-    OPC_FMUL_df     = (0x2 << 22) | OPC_MSA_3RF_1B,
-    OPC_FCUNE_df    = (0x2 << 22) | OPC_MSA_3RF_1C,
-    OPC_FCUEQ_df    = (0x3 << 22) | OPC_MSA_3RF_1A,
-    OPC_FDIV_df     = (0x3 << 22) | OPC_MSA_3RF_1B,
-    OPC_FCNE_df     = (0x3 << 22) | OPC_MSA_3RF_1C,
-    OPC_FCLT_df     = (0x4 << 22) | OPC_MSA_3RF_1A,
-    OPC_FMADD_df    = (0x4 << 22) | OPC_MSA_3RF_1B,
-    OPC_FCULT_df    = (0x5 << 22) | OPC_MSA_3RF_1A,
-    OPC_FMSUB_df    = (0x5 << 22) | OPC_MSA_3RF_1B,
-    OPC_FCLE_df     = (0x6 << 22) | OPC_MSA_3RF_1A,
-    OPC_FCULE_df    = (0x7 << 22) | OPC_MSA_3RF_1A,
-    OPC_FEXP2_df    = (0x7 << 22) | OPC_MSA_3RF_1B,
-    OPC_FSAF_df     = (0x8 << 22) | OPC_MSA_3RF_1A,
-    OPC_FEXDO_df    = (0x8 << 22) | OPC_MSA_3RF_1B,
-    OPC_FSUN_df     = (0x9 << 22) | OPC_MSA_3RF_1A,
-    OPC_FSOR_df     = (0x9 << 22) | OPC_MSA_3RF_1C,
-    OPC_FSEQ_df     = (0xA << 22) | OPC_MSA_3RF_1A,
-    OPC_FTQ_df      = (0xA << 22) | OPC_MSA_3RF_1B,
-    OPC_FSUNE_df    = (0xA << 22) | OPC_MSA_3RF_1C,
-    OPC_FSUEQ_df    = (0xB << 22) | OPC_MSA_3RF_1A,
-    OPC_FSNE_df     = (0xB << 22) | OPC_MSA_3RF_1C,
-    OPC_FSLT_df     = (0xC << 22) | OPC_MSA_3RF_1A,
-    OPC_FMIN_df     = (0xC << 22) | OPC_MSA_3RF_1B,
-    OPC_FSULT_df    = (0xD << 22) | OPC_MSA_3RF_1A,
-    OPC_FMIN_A_df   = (0xD << 22) | OPC_MSA_3RF_1B,
-    OPC_FSLE_df     = (0xE << 22) | OPC_MSA_3RF_1A,
-    OPC_FMAX_df     = (0xE << 22) | OPC_MSA_3RF_1B,
-    OPC_FSULE_df    = (0xF << 22) | OPC_MSA_3RF_1A,
-    OPC_FMAX_A_df   = (0xF << 22) | OPC_MSA_3RF_1B,
 };
 
 static const char msaregnames[][6] = {
@@ -1669,144 +1629,50 @@ static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a,
     return true;
 }
 
+TRANS_DF(FCAF,      trans_msa_3rf, DF_WORD, gen_helper_msa_fcaf_df);
+TRANS_DF(FCUN,      trans_msa_3rf, DF_WORD, gen_helper_msa_fcun_df);
+TRANS_DF(FCEQ,      trans_msa_3rf, DF_WORD, gen_helper_msa_fceq_df);
+TRANS_DF(FCUEQ,     trans_msa_3rf, DF_WORD, gen_helper_msa_fcueq_df);
+TRANS_DF(FCLT,      trans_msa_3rf, DF_WORD, gen_helper_msa_fclt_df);
+TRANS_DF(FCULT,     trans_msa_3rf, DF_WORD, gen_helper_msa_fcult_df);
+TRANS_DF(FCLE,      trans_msa_3rf, DF_WORD, gen_helper_msa_fcle_df);
+TRANS_DF(FCULE,     trans_msa_3rf, DF_WORD, gen_helper_msa_fcule_df);
+TRANS_DF(FSAF,      trans_msa_3rf, DF_WORD, gen_helper_msa_fsaf_df);
+TRANS_DF(FSUN,      trans_msa_3rf, DF_WORD, gen_helper_msa_fsun_df);
+TRANS_DF(FSEQ,      trans_msa_3rf, DF_WORD, gen_helper_msa_fseq_df);
+TRANS_DF(FSUEQ,     trans_msa_3rf, DF_WORD, gen_helper_msa_fsueq_df);
+TRANS_DF(FSLT,      trans_msa_3rf, DF_WORD, gen_helper_msa_fslt_df);
+TRANS_DF(FSULT,     trans_msa_3rf, DF_WORD, gen_helper_msa_fsult_df);
+TRANS_DF(FSLE,      trans_msa_3rf, DF_WORD, gen_helper_msa_fsle_df);
+TRANS_DF(FSULE,     trans_msa_3rf, DF_WORD, gen_helper_msa_fsule_df);
+
+TRANS_DF(FADD,      trans_msa_3rf, DF_WORD, gen_helper_msa_fadd_df);
+TRANS_DF(FSUB,      trans_msa_3rf, DF_WORD, gen_helper_msa_fsub_df);
+TRANS_DF(FMUL,      trans_msa_3rf, DF_WORD, gen_helper_msa_fmul_df);
+TRANS_DF(FDIV,      trans_msa_3rf, DF_WORD, gen_helper_msa_fdiv_df);
+TRANS_DF(FMADD,     trans_msa_3rf, DF_WORD, gen_helper_msa_fmadd_df);
+TRANS_DF(FMSUB,     trans_msa_3rf, DF_WORD, gen_helper_msa_fmsub_df);
+TRANS_DF(FEXP2,     trans_msa_3rf, DF_WORD, gen_helper_msa_fexp2_df);
+TRANS_DF(FEXDO,     trans_msa_3rf, DF_WORD, gen_helper_msa_fexdo_df);
+TRANS_DF(FTQ,       trans_msa_3rf, DF_WORD, gen_helper_msa_ftq_df);
+TRANS_DF(FMIN,      trans_msa_3rf, DF_WORD, gen_helper_msa_fmin_df);
+TRANS_DF(FMIN_A,    trans_msa_3rf, DF_WORD, gen_helper_msa_fmin_a_df);
+TRANS_DF(FMAX,      trans_msa_3rf, DF_WORD, gen_helper_msa_fmax_df);
+TRANS_DF(FMAX_A,    trans_msa_3rf, DF_WORD, gen_helper_msa_fmax_a_df);
+
+TRANS_DF(FCOR,      trans_msa_3rf, DF_WORD, gen_helper_msa_fcor_df);
+TRANS_DF(FCUNE,     trans_msa_3rf, DF_WORD, gen_helper_msa_fcune_df);
+TRANS_DF(FCNE,      trans_msa_3rf, DF_WORD, gen_helper_msa_fcne_df);
 TRANS_DF(MUL_Q,     trans_msa_3rf, DF_HALF, gen_helper_msa_mul_q_df);
 TRANS_DF(MADD_Q,    trans_msa_3rf, DF_HALF, gen_helper_msa_madd_q_df);
 TRANS_DF(MSUB_Q,    trans_msa_3rf, DF_HALF, gen_helper_msa_msub_q_df);
+TRANS_DF(FSOR,      trans_msa_3rf, DF_WORD, gen_helper_msa_fsor_df);
+TRANS_DF(FSUNE,     trans_msa_3rf, DF_WORD, gen_helper_msa_fsune_df);
+TRANS_DF(FSNE,      trans_msa_3rf, DF_WORD, gen_helper_msa_fsne_df);
 TRANS_DF(MULR_Q,    trans_msa_3rf, DF_HALF, gen_helper_msa_mulr_q_df);
 TRANS_DF(MADDR_Q,   trans_msa_3rf, DF_HALF, gen_helper_msa_maddr_q_df);
 TRANS_DF(MSUBR_Q,   trans_msa_3rf, DF_HALF, gen_helper_msa_msubr_q_df);
 
-static void gen_msa_3rf(DisasContext *ctx)
-{
-#define MASK_MSA_3RF(op)    (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
-    uint8_t df = (ctx->opcode >> 21) & 0x1;
-    uint8_t wt = (ctx->opcode >> 16) & 0x1f;
-    uint8_t ws = (ctx->opcode >> 11) & 0x1f;
-    uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-
-    TCGv_i32 twd = tcg_const_i32(wd);
-    TCGv_i32 tws = tcg_const_i32(ws);
-    TCGv_i32 twt = tcg_const_i32(wt);
-    /* adjust df value for floating-point instruction */
-    TCGv_i32 tdf = tcg_constant_i32(DF_WORD + df);
-
-    switch (MASK_MSA_3RF(ctx->opcode)) {
-    case OPC_FCAF_df:
-        gen_helper_msa_fcaf_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FADD_df:
-        gen_helper_msa_fadd_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FCUN_df:
-        gen_helper_msa_fcun_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FSUB_df:
-        gen_helper_msa_fsub_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FCOR_df:
-        gen_helper_msa_fcor_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FCEQ_df:
-        gen_helper_msa_fceq_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FMUL_df:
-        gen_helper_msa_fmul_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FCUNE_df:
-        gen_helper_msa_fcune_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FCUEQ_df:
-        gen_helper_msa_fcueq_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FDIV_df:
-        gen_helper_msa_fdiv_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FCNE_df:
-        gen_helper_msa_fcne_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FCLT_df:
-        gen_helper_msa_fclt_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FMADD_df:
-        gen_helper_msa_fmadd_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FCULT_df:
-        gen_helper_msa_fcult_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FMSUB_df:
-        gen_helper_msa_fmsub_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FCLE_df:
-        gen_helper_msa_fcle_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FCULE_df:
-        gen_helper_msa_fcule_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FEXP2_df:
-        gen_helper_msa_fexp2_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FSAF_df:
-        gen_helper_msa_fsaf_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FEXDO_df:
-        gen_helper_msa_fexdo_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FSUN_df:
-        gen_helper_msa_fsun_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FSOR_df:
-        gen_helper_msa_fsor_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FSEQ_df:
-        gen_helper_msa_fseq_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FTQ_df:
-        gen_helper_msa_ftq_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FSUNE_df:
-        gen_helper_msa_fsune_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FSUEQ_df:
-        gen_helper_msa_fsueq_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FSNE_df:
-        gen_helper_msa_fsne_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FSLT_df:
-        gen_helper_msa_fslt_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FMIN_df:
-        gen_helper_msa_fmin_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FSULT_df:
-        gen_helper_msa_fsult_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FMIN_A_df:
-        gen_helper_msa_fmin_a_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FSLE_df:
-        gen_helper_msa_fsle_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FMAX_df:
-        gen_helper_msa_fmax_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FSULE_df:
-        gen_helper_msa_fsule_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_FMAX_A_df:
-        gen_helper_msa_fmax_a_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    default:
-        MIPS_INVAL("MSA instruction");
-        gen_reserved_instruction(ctx);
-        break;
-    }
-
-    tcg_temp_free_i32(twd);
-    tcg_temp_free_i32(tws);
-    tcg_temp_free_i32(twt);
-}
-
 static bool trans_msa_2r(DisasContext *ctx, arg_msa_r *a,
                          void (*gen_msa_2r_b)(TCGv_ptr, TCGv_i32, TCGv_i32),
                          void (*gen_msa_2r_h)(TCGv_ptr, TCGv_i32, TCGv_i32),
@@ -1955,11 +1821,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
     case OPC_MSA_ELM:
         gen_msa_elm(ctx);
         break;
-    case OPC_MSA_3RF_1A:
-    case OPC_MSA_3RF_1B:
-    case OPC_MSA_3RF_1C:
-        gen_msa_3rf(ctx);
-        break;
     default:
         MIPS_INVAL("MSA instruction");
         gen_reserved_instruction(ctx);
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 22/33] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (20 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 21/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-24 17:51   ` Richard Henderson
  2021-10-24 17:52   ` Richard Henderson
  2021-10-23 21:47 ` [PATCH 23/33] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Philippe Mathieu-Daudé
                   ` (11 subsequent siblings)
  33 siblings, 2 replies; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Convert 3-register operations to decodetree.

Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      |  6 ++++++
 target/mips/tcg/msa_translate.c | 35 ++++++++++++++++++++++-----------
 2 files changed, 29 insertions(+), 12 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 28b7a71d930..ca0fd568560 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -24,6 +24,7 @@
 @vec                ...... .....     wt:5 ws:5 wd:5 ......  &msa_r df=0
 @2r                 ...... ........  df:2 ws:5 wd:5 ......  &msa_r wt=0
 @2rf                ...... ......... df:1 ws:5 wd:5 ......  &msa_r wt=0
+@3r                 ...... ...  df:2 wt:5 ws:5 wd:5 ......  &msa_r
 @3rf                ...... .... df:1 wt:5 ws:5 wd:5 ......  &msa_r
 @u5                 ...... ... df:2 sa:5  ws:5 wd:5 ......  &msa_ldst
 @s5                 ...... ... df:2 sa:s5 ws:5 wd:5 ......  &msa_ldst
@@ -79,6 +80,11 @@ BNZ                 010001 111 .. ..... ................    @bz
   SRARI             011110 010 ....... ..... .....  001010  @bit
   SRLRI             011110 011 ....... ..... .....  001010  @bit
 
+  SLD               011110 000 .. ..... ..... ..... 010100  @3r
+  SPLAT             011110 001 .. ..... ..... ..... 010100  @3r
+
+  VSHF              011110 000 .. ..... ..... ..... 010101  @3r
+
   FCAF              011110 0000 . ..... ..... ..... 011010  @3rf
   FCUN              011110 0001 . ..... ..... ..... 011010  @3rf
   FCEQ              011110 0010 . ..... ..... ..... 011010  @3rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 4543b7abdfb..0c7055c68bd 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -45,15 +45,12 @@ enum {
     OPC_SUBS_S_df   = (0x0 << 23) | OPC_MSA_3R_11,
     OPC_MULV_df     = (0x0 << 23) | OPC_MSA_3R_12,
     OPC_DOTP_S_df   = (0x0 << 23) | OPC_MSA_3R_13,
-    OPC_SLD_df      = (0x0 << 23) | OPC_MSA_3R_14,
-    OPC_VSHF_df     = (0x0 << 23) | OPC_MSA_3R_15,
     OPC_SRA_df      = (0x1 << 23) | OPC_MSA_3R_0D,
     OPC_SUBV_df     = (0x1 << 23) | OPC_MSA_3R_0E,
     OPC_ADDS_A_df   = (0x1 << 23) | OPC_MSA_3R_10,
     OPC_SUBS_U_df   = (0x1 << 23) | OPC_MSA_3R_11,
     OPC_MADDV_df    = (0x1 << 23) | OPC_MSA_3R_12,
     OPC_DOTP_U_df   = (0x1 << 23) | OPC_MSA_3R_13,
-    OPC_SPLAT_df    = (0x1 << 23) | OPC_MSA_3R_14,
     OPC_SRAR_df     = (0x1 << 23) | OPC_MSA_3R_15,
     OPC_SRL_df      = (0x2 << 23) | OPC_MSA_3R_0D,
     OPC_MAX_S_df    = (0x2 << 23) | OPC_MSA_3R_0E,
@@ -469,6 +466,29 @@ TRANS_MSA(SAT_U,    trans_msa_bit, gen_helper_msa_sat_u_df);
 TRANS_MSA(SRARI,    trans_msa_bit, gen_helper_msa_srari_df);
 TRANS_MSA(SRLRI,    trans_msa_bit, gen_helper_msa_srlri_df);
 
+static bool trans_msa_3r_df(DisasContext *ctx, arg_msa_r *a,
+                            void (*gen_msa_3r_df)(TCGv_ptr, TCGv_i32, TCGv_i32,
+                                                  TCGv_i32, TCGv_i32))
+{
+    TCGv_i32 tdf = tcg_constant_i32(a->df);
+    TCGv_i32 twd = tcg_const_i32(a->wd);
+    TCGv_i32 tws = tcg_const_i32(a->ws);
+    TCGv_i32 twt = tcg_const_i32(a->wt);
+
+    gen_msa_3r_df(cpu_env, tdf, twd, tws, twt);
+
+    tcg_temp_free_i32(twd);
+    tcg_temp_free_i32(tws);
+    tcg_temp_free_i32(twt);
+
+    return true;
+}
+
+TRANS_MSA(SLD,          trans_msa_3r_df, gen_helper_msa_sld_df);
+TRANS_MSA(SPLAT,        trans_msa_3r_df, gen_helper_msa_splat_df);
+
+TRANS_MSA(VSHF,         trans_msa_3r_df, gen_helper_msa_vshf_df);
+
 static void gen_msa_3r(DisasContext *ctx)
 {
 #define MASK_MSA_3R(op)    (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
@@ -1219,12 +1239,6 @@ static void gen_msa_3r(DisasContext *ctx)
             break;
         }
         break;
-    case OPC_SLD_df:
-        gen_helper_msa_sld_df(cpu_env, tdf, twd, tws, twt);
-        break;
-    case OPC_VSHF_df:
-        gen_helper_msa_vshf_df(cpu_env, tdf, twd, tws, twt);
-        break;
     case OPC_SUBV_df:
         switch (df) {
         case DF_BYTE:
@@ -1257,9 +1271,6 @@ static void gen_msa_3r(DisasContext *ctx)
             break;
         }
         break;
-    case OPC_SPLAT_df:
-        gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt);
-        break;
     case OPC_SUBSUS_U_df:
         switch (df) {
         case DF_BYTE:
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 23/33] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (21 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 22/33] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-24 17:55   ` Richard Henderson
  2021-10-23 21:47 ` [PATCH 24/33] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) Philippe Mathieu-Daudé
                   ` (10 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Convert 3-register operations to decodetree.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      |  11 ++
 target/mips/tcg/msa_translate.c | 213 +++++++++-----------------------
 2 files changed, 66 insertions(+), 158 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index ca0fd568560..4a9cf85fa7a 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -80,10 +80,21 @@ BNZ                 010001 111 .. ..... ................    @bz
   SRARI             011110 010 ....... ..... .....  001010  @bit
   SRLRI             011110 011 ....... ..... .....  001010  @bit
 
+  DOTP_S            011110 000.. ..... ..... .....  010011  @3r
+  DOTP_U            011110 001.. ..... ..... .....  010011  @3r
+  DPADD_S           011110 010.. ..... ..... .....  010011  @3r
+  DPADD_U           011110 011.. ..... ..... .....  010011  @3r
+  DPSUB_S           011110 100.. ..... ..... .....  010011  @3r
+  DPSUB_U           011110 101.. ..... ..... .....  010011  @3r
+
   SLD               011110 000 .. ..... ..... ..... 010100  @3r
   SPLAT             011110 001 .. ..... ..... ..... 010100  @3r
 
   VSHF              011110 000 .. ..... ..... ..... 010101  @3r
+  HADD_S            011110 100.. ..... ..... .....  010101  @3r
+  HADD_U            011110 101.. ..... ..... .....  010101  @3r
+  HSUB_S            011110 110.. ..... ..... .....  010101  @3r
+  HSUB_U            011110 111.. ..... ..... .....  010101  @3r
 
   FCAF              011110 0000 . ..... ..... ..... 011010  @3rf
   FCUN              011110 0001 . ..... ..... ..... 011010  @3rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 0c7055c68bd..e1da532e5c9 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -44,13 +44,11 @@ enum {
     OPC_ADD_A_df    = (0x0 << 23) | OPC_MSA_3R_10,
     OPC_SUBS_S_df   = (0x0 << 23) | OPC_MSA_3R_11,
     OPC_MULV_df     = (0x0 << 23) | OPC_MSA_3R_12,
-    OPC_DOTP_S_df   = (0x0 << 23) | OPC_MSA_3R_13,
     OPC_SRA_df      = (0x1 << 23) | OPC_MSA_3R_0D,
     OPC_SUBV_df     = (0x1 << 23) | OPC_MSA_3R_0E,
     OPC_ADDS_A_df   = (0x1 << 23) | OPC_MSA_3R_10,
     OPC_SUBS_U_df   = (0x1 << 23) | OPC_MSA_3R_11,
     OPC_MADDV_df    = (0x1 << 23) | OPC_MSA_3R_12,
-    OPC_DOTP_U_df   = (0x1 << 23) | OPC_MSA_3R_13,
     OPC_SRAR_df     = (0x1 << 23) | OPC_MSA_3R_15,
     OPC_SRL_df      = (0x2 << 23) | OPC_MSA_3R_0D,
     OPC_MAX_S_df    = (0x2 << 23) | OPC_MSA_3R_0E,
@@ -58,7 +56,6 @@ enum {
     OPC_ADDS_S_df   = (0x2 << 23) | OPC_MSA_3R_10,
     OPC_SUBSUS_U_df = (0x2 << 23) | OPC_MSA_3R_11,
     OPC_MSUBV_df    = (0x2 << 23) | OPC_MSA_3R_12,
-    OPC_DPADD_S_df  = (0x2 << 23) | OPC_MSA_3R_13,
     OPC_PCKEV_df    = (0x2 << 23) | OPC_MSA_3R_14,
     OPC_SRLR_df     = (0x2 << 23) | OPC_MSA_3R_15,
     OPC_BCLR_df     = (0x3 << 23) | OPC_MSA_3R_0D,
@@ -66,7 +63,6 @@ enum {
     OPC_CLT_U_df    = (0x3 << 23) | OPC_MSA_3R_0F,
     OPC_ADDS_U_df   = (0x3 << 23) | OPC_MSA_3R_10,
     OPC_SUBSUU_S_df = (0x3 << 23) | OPC_MSA_3R_11,
-    OPC_DPADD_U_df  = (0x3 << 23) | OPC_MSA_3R_13,
     OPC_PCKOD_df    = (0x3 << 23) | OPC_MSA_3R_14,
     OPC_BSET_df     = (0x4 << 23) | OPC_MSA_3R_0D,
     OPC_MIN_S_df    = (0x4 << 23) | OPC_MSA_3R_0E,
@@ -74,30 +70,24 @@ enum {
     OPC_AVE_S_df    = (0x4 << 23) | OPC_MSA_3R_10,
     OPC_ASUB_S_df   = (0x4 << 23) | OPC_MSA_3R_11,
     OPC_DIV_S_df    = (0x4 << 23) | OPC_MSA_3R_12,
-    OPC_DPSUB_S_df  = (0x4 << 23) | OPC_MSA_3R_13,
     OPC_ILVL_df     = (0x4 << 23) | OPC_MSA_3R_14,
-    OPC_HADD_S_df   = (0x4 << 23) | OPC_MSA_3R_15,
     OPC_BNEG_df     = (0x5 << 23) | OPC_MSA_3R_0D,
     OPC_MIN_U_df    = (0x5 << 23) | OPC_MSA_3R_0E,
     OPC_CLE_U_df    = (0x5 << 23) | OPC_MSA_3R_0F,
     OPC_AVE_U_df    = (0x5 << 23) | OPC_MSA_3R_10,
     OPC_ASUB_U_df   = (0x5 << 23) | OPC_MSA_3R_11,
     OPC_DIV_U_df    = (0x5 << 23) | OPC_MSA_3R_12,
-    OPC_DPSUB_U_df  = (0x5 << 23) | OPC_MSA_3R_13,
     OPC_ILVR_df     = (0x5 << 23) | OPC_MSA_3R_14,
-    OPC_HADD_U_df   = (0x5 << 23) | OPC_MSA_3R_15,
     OPC_BINSL_df    = (0x6 << 23) | OPC_MSA_3R_0D,
     OPC_MAX_A_df    = (0x6 << 23) | OPC_MSA_3R_0E,
     OPC_AVER_S_df   = (0x6 << 23) | OPC_MSA_3R_10,
     OPC_MOD_S_df    = (0x6 << 23) | OPC_MSA_3R_12,
     OPC_ILVEV_df    = (0x6 << 23) | OPC_MSA_3R_14,
-    OPC_HSUB_S_df   = (0x6 << 23) | OPC_MSA_3R_15,
     OPC_BINSR_df    = (0x7 << 23) | OPC_MSA_3R_0D,
     OPC_MIN_A_df    = (0x7 << 23) | OPC_MSA_3R_0E,
     OPC_AVER_U_df   = (0x7 << 23) | OPC_MSA_3R_10,
     OPC_MOD_U_df    = (0x7 << 23) | OPC_MSA_3R_12,
     OPC_ILVOD_df    = (0x7 << 23) | OPC_MSA_3R_14,
-    OPC_HSUB_U_df   = (0x7 << 23) | OPC_MSA_3R_15,
 
     /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
     OPC_SLDI_df     = (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM,
@@ -209,6 +199,10 @@ static inline bool check_msa_access(DisasContext *ctx)
         TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
                     gen_func##_b, gen_func##_h, gen_func##_w, gen_func##_d)
 
+#define TRANS_DF_B(NAME, trans_func, gen_func) \
+        TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
+                    NULL, gen_func##_h, gen_func##_w, gen_func##_d)
+
 static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
                                    TCGCond cond)
 {
@@ -484,10 +478,61 @@ static bool trans_msa_3r_df(DisasContext *ctx, arg_msa_r *a,
     return true;
 }
 
+static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a,
+                         void (*gen_msa_3r_b)(TCGv_ptr, TCGv_i32,
+                                              TCGv_i32, TCGv_i32),
+                         void (*gen_msa_3r_h)(TCGv_ptr, TCGv_i32,
+                                              TCGv_i32, TCGv_i32),
+                         void (*gen_msa_3r_w)(TCGv_ptr, TCGv_i32,
+                                              TCGv_i32, TCGv_i32),
+                         void (*gen_msa_3r_d)(TCGv_ptr, TCGv_i32,
+                                              TCGv_i32, TCGv_i32))
+{
+    TCGv_i32 twd = tcg_const_i32(a->wd);
+    TCGv_i32 tws = tcg_const_i32(a->ws);
+    TCGv_i32 twt = tcg_const_i32(a->wt);
+
+    switch (a->df) {
+    case DF_BYTE:
+        if (gen_msa_3r_b == NULL) {
+            gen_reserved_instruction(ctx);
+        } else {
+            gen_msa_3r_b(cpu_env, twd, tws, twt);
+        }
+        break;
+    case DF_HALF:
+        gen_msa_3r_h(cpu_env, twd, tws, twt);
+        break;
+    case DF_WORD:
+        gen_msa_3r_w(cpu_env, twd, tws, twt);
+        break;
+    case DF_DOUBLE:
+        gen_msa_3r_d(cpu_env, twd, tws, twt);
+        break;
+    }
+
+    tcg_temp_free_i32(twt);
+    tcg_temp_free_i32(tws);
+    tcg_temp_free_i32(twd);
+
+    return true;
+}
+
+TRANS_DF_B(DOTP_S,      trans_msa_3r,    gen_helper_msa_dotp_s);
+TRANS_DF_B(DOTP_U,      trans_msa_3r,    gen_helper_msa_dotp_u);
+TRANS_DF_B(DPADD_S,     trans_msa_3r,    gen_helper_msa_dpadd_s);
+TRANS_DF_B(DPADD_U,     trans_msa_3r,    gen_helper_msa_dpadd_u);
+TRANS_DF_B(DPSUB_S,     trans_msa_3r,    gen_helper_msa_dpsub_s);
+TRANS_DF_B(DPSUB_U,     trans_msa_3r,    gen_helper_msa_dpsub_u);
+
 TRANS_MSA(SLD,          trans_msa_3r_df, gen_helper_msa_sld_df);
 TRANS_MSA(SPLAT,        trans_msa_3r_df, gen_helper_msa_splat_df);
 
 TRANS_MSA(VSHF,         trans_msa_3r_df, gen_helper_msa_vshf_df);
+TRANS_DF_B(HADD_S,      trans_msa_3r,    gen_helper_msa_hadd_s);
+TRANS_DF_B(HADD_U,      trans_msa_3r,    gen_helper_msa_hadd_u);
+TRANS_DF_B(HSUB_S,      trans_msa_3r,    gen_helper_msa_hsub_s);
+TRANS_DF_B(HSUB_U,      trans_msa_3r,    gen_helper_msa_hsub_u);
 
 static void gen_msa_3r(DisasContext *ctx)
 {
@@ -1303,154 +1348,6 @@ static void gen_msa_3r(DisasContext *ctx)
             break;
         }
         break;
-
-    case OPC_DOTP_S_df:
-    case OPC_DOTP_U_df:
-    case OPC_DPADD_S_df:
-    case OPC_DPADD_U_df:
-    case OPC_DPSUB_S_df:
-    case OPC_HADD_S_df:
-    case OPC_DPSUB_U_df:
-    case OPC_HADD_U_df:
-    case OPC_HSUB_S_df:
-    case OPC_HSUB_U_df:
-        if (df == DF_BYTE) {
-            gen_reserved_instruction(ctx);
-            break;
-        }
-        switch (MASK_MSA_3R(ctx->opcode)) {
-        case OPC_HADD_S_df:
-            switch (df) {
-            case DF_HALF:
-                gen_helper_msa_hadd_s_h(cpu_env, twd, tws, twt);
-                break;
-            case DF_WORD:
-                gen_helper_msa_hadd_s_w(cpu_env, twd, tws, twt);
-                break;
-            case DF_DOUBLE:
-                gen_helper_msa_hadd_s_d(cpu_env, twd, tws, twt);
-                break;
-            }
-            break;
-        case OPC_HADD_U_df:
-            switch (df) {
-            case DF_HALF:
-                gen_helper_msa_hadd_u_h(cpu_env, twd, tws, twt);
-                break;
-            case DF_WORD:
-                gen_helper_msa_hadd_u_w(cpu_env, twd, tws, twt);
-                break;
-            case DF_DOUBLE:
-                gen_helper_msa_hadd_u_d(cpu_env, twd, tws, twt);
-                break;
-            }
-            break;
-        case OPC_HSUB_S_df:
-            switch (df) {
-            case DF_HALF:
-                gen_helper_msa_hsub_s_h(cpu_env, twd, tws, twt);
-                break;
-            case DF_WORD:
-                gen_helper_msa_hsub_s_w(cpu_env, twd, tws, twt);
-                break;
-            case DF_DOUBLE:
-                gen_helper_msa_hsub_s_d(cpu_env, twd, tws, twt);
-                break;
-            }
-            break;
-        case OPC_HSUB_U_df:
-            switch (df) {
-            case DF_HALF:
-                gen_helper_msa_hsub_u_h(cpu_env, twd, tws, twt);
-                break;
-            case DF_WORD:
-                gen_helper_msa_hsub_u_w(cpu_env, twd, tws, twt);
-                break;
-            case DF_DOUBLE:
-                gen_helper_msa_hsub_u_d(cpu_env, twd, tws, twt);
-                break;
-            }
-            break;
-        case OPC_DOTP_S_df:
-            switch (df) {
-            case DF_HALF:
-                gen_helper_msa_dotp_s_h(cpu_env, twd, tws, twt);
-                break;
-            case DF_WORD:
-                gen_helper_msa_dotp_s_w(cpu_env, twd, tws, twt);
-                break;
-            case DF_DOUBLE:
-                gen_helper_msa_dotp_s_d(cpu_env, twd, tws, twt);
-                break;
-            }
-            break;
-        case OPC_DOTP_U_df:
-            switch (df) {
-            case DF_HALF:
-                gen_helper_msa_dotp_u_h(cpu_env, twd, tws, twt);
-                break;
-            case DF_WORD:
-                gen_helper_msa_dotp_u_w(cpu_env, twd, tws, twt);
-                break;
-            case DF_DOUBLE:
-                gen_helper_msa_dotp_u_d(cpu_env, twd, tws, twt);
-                break;
-            }
-            break;
-        case OPC_DPADD_S_df:
-            switch (df) {
-            case DF_HALF:
-                gen_helper_msa_dpadd_s_h(cpu_env, twd, tws, twt);
-                break;
-            case DF_WORD:
-                gen_helper_msa_dpadd_s_w(cpu_env, twd, tws, twt);
-                break;
-            case DF_DOUBLE:
-                gen_helper_msa_dpadd_s_d(cpu_env, twd, tws, twt);
-                break;
-            }
-            break;
-        case OPC_DPADD_U_df:
-            switch (df) {
-            case DF_HALF:
-                gen_helper_msa_dpadd_u_h(cpu_env, twd, tws, twt);
-                break;
-            case DF_WORD:
-                gen_helper_msa_dpadd_u_w(cpu_env, twd, tws, twt);
-                break;
-            case DF_DOUBLE:
-                gen_helper_msa_dpadd_u_d(cpu_env, twd, tws, twt);
-                break;
-            }
-            break;
-        case OPC_DPSUB_S_df:
-            switch (df) {
-            case DF_HALF:
-                gen_helper_msa_dpsub_s_h(cpu_env, twd, tws, twt);
-                break;
-            case DF_WORD:
-                gen_helper_msa_dpsub_s_w(cpu_env, twd, tws, twt);
-                break;
-            case DF_DOUBLE:
-                gen_helper_msa_dpsub_s_d(cpu_env, twd, tws, twt);
-                break;
-            }
-            break;
-        case OPC_DPSUB_U_df:
-            switch (df) {
-            case DF_HALF:
-                gen_helper_msa_dpsub_u_h(cpu_env, twd, tws, twt);
-                break;
-            case DF_WORD:
-                gen_helper_msa_dpsub_u_w(cpu_env, twd, tws, twt);
-                break;
-            case DF_DOUBLE:
-                gen_helper_msa_dpsub_u_d(cpu_env, twd, tws, twt);
-                break;
-            }
-            break;
-        }
-        break;
     default:
         MIPS_INVAL("MSA instruction");
         gen_reserved_instruction(ctx);
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 24/33] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (22 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 23/33] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-24 18:09   ` Richard Henderson
  2021-10-23 21:47 ` [PATCH 25/33] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) Philippe Mathieu-Daudé
                   ` (9 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Convert BINSL (Vector Bit Insert Left) and BINSR (Vector Bit
Insert Right) opcodes to decodetree.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      |  3 +++
 target/mips/tcg/msa_translate.c | 37 +++------------------------------
 2 files changed, 6 insertions(+), 34 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 4a9cf85fa7a..1d6fd86ef3d 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -80,6 +80,9 @@ BNZ                 010001 111 .. ..... ................    @bz
   SRARI             011110 010 ....... ..... .....  001010  @bit
   SRLRI             011110 011 ....... ..... .....  001010  @bit
 
+  BINSL             011110 110.. ..... ..... .....  001101  @3r
+  BINSR             011110 111.. ..... ..... .....  001101  @3r
+
   DOTP_S            011110 000.. ..... ..... .....  010011  @3r
   DOTP_U            011110 001.. ..... ..... .....  010011  @3r
   DPADD_S           011110 010.. ..... ..... .....  010011  @3r
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index e1da532e5c9..1b69ec149a5 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -78,12 +78,10 @@ enum {
     OPC_ASUB_U_df   = (0x5 << 23) | OPC_MSA_3R_11,
     OPC_DIV_U_df    = (0x5 << 23) | OPC_MSA_3R_12,
     OPC_ILVR_df     = (0x5 << 23) | OPC_MSA_3R_14,
-    OPC_BINSL_df    = (0x6 << 23) | OPC_MSA_3R_0D,
     OPC_MAX_A_df    = (0x6 << 23) | OPC_MSA_3R_0E,
     OPC_AVER_S_df   = (0x6 << 23) | OPC_MSA_3R_10,
     OPC_MOD_S_df    = (0x6 << 23) | OPC_MSA_3R_12,
     OPC_ILVEV_df    = (0x6 << 23) | OPC_MSA_3R_14,
-    OPC_BINSR_df    = (0x7 << 23) | OPC_MSA_3R_0D,
     OPC_MIN_A_df    = (0x7 << 23) | OPC_MSA_3R_0E,
     OPC_AVER_U_df   = (0x7 << 23) | OPC_MSA_3R_10,
     OPC_MOD_U_df    = (0x7 << 23) | OPC_MSA_3R_12,
@@ -518,6 +516,9 @@ static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a,
     return true;
 }
 
+TRANS_DF_E(BINSL,       trans_msa_3r,    gen_helper_msa_binsl);
+TRANS_DF_E(BINSR,       trans_msa_3r,    gen_helper_msa_binsr);
+
 TRANS_DF_B(DOTP_S,      trans_msa_3r,    gen_helper_msa_dotp_s);
 TRANS_DF_B(DOTP_U,      trans_msa_3r,    gen_helper_msa_dotp_u);
 TRANS_DF_B(DPADD_S,     trans_msa_3r,    gen_helper_msa_dpadd_s);
@@ -548,38 +549,6 @@ static void gen_msa_3r(DisasContext *ctx)
     TCGv_i32 twt = tcg_const_i32(wt);
 
     switch (MASK_MSA_3R(ctx->opcode)) {
-    case OPC_BINSL_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_binsl_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_binsl_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_binsl_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_binsl_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_BINSR_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_binsr_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_binsr_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_binsr_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_binsr_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
     case OPC_BCLR_df:
         switch (df) {
         case DF_BYTE:
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 25/33] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4)
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (23 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 24/33] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-24 18:12   ` Richard Henderson
  2021-10-23 21:47 ` [PATCH 26/33] target/mips: Convert MSA ELM instruction format to decodetree Philippe Mathieu-Daudé
                   ` (8 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Convert 3-register operations to decodetree.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      |  53 ++
 target/mips/tcg/msa_translate.c | 916 ++------------------------------
 2 files changed, 106 insertions(+), 863 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 1d6fd86ef3d..3d0d9a52675 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -80,9 +80,54 @@ BNZ                 010001 111 .. ..... ................    @bz
   SRARI             011110 010 ....... ..... .....  001010  @bit
   SRLRI             011110 011 ....... ..... .....  001010  @bit
 
+  SLL               011110 000.. ..... ..... .....  001101  @3r
+  SRA               011110 001.. ..... ..... .....  001101  @3r
+  SRL               011110 010.. ..... ..... .....  001101  @3r
+  BCLR              011110 011.. ..... ..... .....  001101  @3r
+  BSET              011110 100.. ..... ..... .....  001101  @3r
+  BNEG              011110 101.. ..... ..... .....  001101  @3r
   BINSL             011110 110.. ..... ..... .....  001101  @3r
   BINSR             011110 111.. ..... ..... .....  001101  @3r
 
+  ADDV              011110 000.. ..... ..... .....  001110  @3r
+  SUBV              011110 001.. ..... ..... .....  001110  @3r
+  MAX_S             011110 010.. ..... ..... .....  001110  @3r
+  MAX_U             011110 011.. ..... ..... .....  001110  @3r
+  MIN_S             011110 100.. ..... ..... .....  001110  @3r
+  MIN_U             011110 101.. ..... ..... .....  001110  @3r
+  MAX_A             011110 110.. ..... ..... .....  001110  @3r
+  MIN_A             011110 111.. ..... ..... .....  001110  @3r
+
+  CEQ               011110 000.. ..... ..... .....  001111  @3r
+  CLT_S             011110 010.. ..... ..... .....  001111  @3r
+  CLT_U             011110 011.. ..... ..... .....  001111  @3r
+  CLE_S             011110 100.. ..... ..... .....  001111  @3r
+  CLE_U             011110 101.. ..... ..... .....  001111  @3r
+
+  ADD_A             011110 000.. ..... ..... .....  010000  @3r
+  ADDS_A            011110 001.. ..... ..... .....  010000  @3r
+  ADDS_S            011110 010.. ..... ..... .....  010000  @3r
+  ADDS_U            011110 011.. ..... ..... .....  010000  @3r
+  AVE_S             011110 100.. ..... ..... .....  010000  @3r
+  AVE_U             011110 101.. ..... ..... .....  010000  @3r
+  AVER_S            011110 110.. ..... ..... .....  010000  @3r
+  AVER_U            011110 111.. ..... ..... .....  010000  @3r
+
+  SUBS_S            011110 000.. ..... ..... .....  010001  @3r
+  SUBS_U            011110 001.. ..... ..... .....  010001  @3r
+  SUBSUS_U          011110 010.. ..... ..... .....  010001  @3r
+  SUBSUU_S          011110 011.. ..... ..... .....  010001  @3r
+  ASUB_S            011110 100.. ..... ..... .....  010001  @3r
+  ASUB_U            011110 101.. ..... ..... .....  010001  @3r
+
+  MULV              011110 000.. ..... ..... .....  010010  @3r
+  MADDV             011110 001.. ..... ..... .....  010010  @3r
+  MSUBV             011110 010.. ..... ..... .....  010010  @3r
+  DIV_S             011110 100.. ..... ..... .....  010010  @3r
+  DIV_U             011110 101.. ..... ..... .....  010010  @3r
+  MOD_S             011110 110.. ..... ..... .....  010010  @3r
+  MOD_U             011110 111.. ..... ..... .....  010010  @3r
+
   DOTP_S            011110 000.. ..... ..... .....  010011  @3r
   DOTP_U            011110 001.. ..... ..... .....  010011  @3r
   DPADD_S           011110 010.. ..... ..... .....  010011  @3r
@@ -92,8 +137,16 @@ BNZ                 010001 111 .. ..... ................    @bz
 
   SLD               011110 000 .. ..... ..... ..... 010100  @3r
   SPLAT             011110 001 .. ..... ..... ..... 010100  @3r
+  PCKEV             011110 010 .. ..... ..... ..... 010100  @3r
+  PCKOD             011110 011 .. ..... ..... ..... 010100  @3r
+  ILVL              011110 100 .. ..... ..... ..... 010100  @3r
+  ILVR              011110 101 .. ..... ..... ..... 010100  @3r
+  ILVEV             011110 110 .. ..... ..... ..... 010100  @3r
+  ILVOD             011110 111 .. ..... ..... ..... 010100  @3r
 
   VSHF              011110 000 .. ..... ..... ..... 010101  @3r
+  SRAR              011110 001 .. ..... ..... ..... 010101  @3r
+  SRLR              011110 010 .. ..... ..... ..... 010101  @3r
   HADD_S            011110 100.. ..... ..... .....  010101  @3r
   HADD_U            011110 101.. ..... ..... .....  010101  @3r
   HSUB_S            011110 110.. ..... ..... .....  010101  @3r
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 1b69ec149a5..7813c126069 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -24,69 +24,10 @@
 
 #define MASK_MSA_MINOR(op)          (MASK_OP_MAJOR(op) | (op & 0x3F))
 enum {
-    OPC_MSA_3R_0D   = 0x0D | OPC_MSA,
-    OPC_MSA_3R_0E   = 0x0E | OPC_MSA,
-    OPC_MSA_3R_0F   = 0x0F | OPC_MSA,
-    OPC_MSA_3R_10   = 0x10 | OPC_MSA,
-    OPC_MSA_3R_11   = 0x11 | OPC_MSA,
-    OPC_MSA_3R_12   = 0x12 | OPC_MSA,
-    OPC_MSA_3R_13   = 0x13 | OPC_MSA,
-    OPC_MSA_3R_14   = 0x14 | OPC_MSA,
-    OPC_MSA_3R_15   = 0x15 | OPC_MSA,
     OPC_MSA_ELM     = 0x19 | OPC_MSA,
 };
 
 enum {
-    /* 3R instruction df(bits 22..21) = _b, _h, _w, d */
-    OPC_SLL_df      = (0x0 << 23) | OPC_MSA_3R_0D,
-    OPC_ADDV_df     = (0x0 << 23) | OPC_MSA_3R_0E,
-    OPC_CEQ_df      = (0x0 << 23) | OPC_MSA_3R_0F,
-    OPC_ADD_A_df    = (0x0 << 23) | OPC_MSA_3R_10,
-    OPC_SUBS_S_df   = (0x0 << 23) | OPC_MSA_3R_11,
-    OPC_MULV_df     = (0x0 << 23) | OPC_MSA_3R_12,
-    OPC_SRA_df      = (0x1 << 23) | OPC_MSA_3R_0D,
-    OPC_SUBV_df     = (0x1 << 23) | OPC_MSA_3R_0E,
-    OPC_ADDS_A_df   = (0x1 << 23) | OPC_MSA_3R_10,
-    OPC_SUBS_U_df   = (0x1 << 23) | OPC_MSA_3R_11,
-    OPC_MADDV_df    = (0x1 << 23) | OPC_MSA_3R_12,
-    OPC_SRAR_df     = (0x1 << 23) | OPC_MSA_3R_15,
-    OPC_SRL_df      = (0x2 << 23) | OPC_MSA_3R_0D,
-    OPC_MAX_S_df    = (0x2 << 23) | OPC_MSA_3R_0E,
-    OPC_CLT_S_df    = (0x2 << 23) | OPC_MSA_3R_0F,
-    OPC_ADDS_S_df   = (0x2 << 23) | OPC_MSA_3R_10,
-    OPC_SUBSUS_U_df = (0x2 << 23) | OPC_MSA_3R_11,
-    OPC_MSUBV_df    = (0x2 << 23) | OPC_MSA_3R_12,
-    OPC_PCKEV_df    = (0x2 << 23) | OPC_MSA_3R_14,
-    OPC_SRLR_df     = (0x2 << 23) | OPC_MSA_3R_15,
-    OPC_BCLR_df     = (0x3 << 23) | OPC_MSA_3R_0D,
-    OPC_MAX_U_df    = (0x3 << 23) | OPC_MSA_3R_0E,
-    OPC_CLT_U_df    = (0x3 << 23) | OPC_MSA_3R_0F,
-    OPC_ADDS_U_df   = (0x3 << 23) | OPC_MSA_3R_10,
-    OPC_SUBSUU_S_df = (0x3 << 23) | OPC_MSA_3R_11,
-    OPC_PCKOD_df    = (0x3 << 23) | OPC_MSA_3R_14,
-    OPC_BSET_df     = (0x4 << 23) | OPC_MSA_3R_0D,
-    OPC_MIN_S_df    = (0x4 << 23) | OPC_MSA_3R_0E,
-    OPC_CLE_S_df    = (0x4 << 23) | OPC_MSA_3R_0F,
-    OPC_AVE_S_df    = (0x4 << 23) | OPC_MSA_3R_10,
-    OPC_ASUB_S_df   = (0x4 << 23) | OPC_MSA_3R_11,
-    OPC_DIV_S_df    = (0x4 << 23) | OPC_MSA_3R_12,
-    OPC_ILVL_df     = (0x4 << 23) | OPC_MSA_3R_14,
-    OPC_BNEG_df     = (0x5 << 23) | OPC_MSA_3R_0D,
-    OPC_MIN_U_df    = (0x5 << 23) | OPC_MSA_3R_0E,
-    OPC_CLE_U_df    = (0x5 << 23) | OPC_MSA_3R_0F,
-    OPC_AVE_U_df    = (0x5 << 23) | OPC_MSA_3R_10,
-    OPC_ASUB_U_df   = (0x5 << 23) | OPC_MSA_3R_11,
-    OPC_DIV_U_df    = (0x5 << 23) | OPC_MSA_3R_12,
-    OPC_ILVR_df     = (0x5 << 23) | OPC_MSA_3R_14,
-    OPC_MAX_A_df    = (0x6 << 23) | OPC_MSA_3R_0E,
-    OPC_AVER_S_df   = (0x6 << 23) | OPC_MSA_3R_10,
-    OPC_MOD_S_df    = (0x6 << 23) | OPC_MSA_3R_12,
-    OPC_ILVEV_df    = (0x6 << 23) | OPC_MSA_3R_14,
-    OPC_MIN_A_df    = (0x7 << 23) | OPC_MSA_3R_0E,
-    OPC_AVER_U_df   = (0x7 << 23) | OPC_MSA_3R_10,
-    OPC_MOD_U_df    = (0x7 << 23) | OPC_MSA_3R_12,
-    OPC_ILVOD_df    = (0x7 << 23) | OPC_MSA_3R_14,
-
     /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
     OPC_SLDI_df     = (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM,
     OPC_CTCMSA      = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
@@ -516,9 +457,54 @@ static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a,
     return true;
 }
 
+TRANS_DF_E(SLL,         trans_msa_3r,    gen_helper_msa_sll);
+TRANS_DF_E(SRA,         trans_msa_3r,    gen_helper_msa_sra);
+TRANS_DF_E(SRL,         trans_msa_3r,    gen_helper_msa_srl);
+TRANS_DF_E(BCLR,        trans_msa_3r,    gen_helper_msa_bclr);
+TRANS_DF_E(BSET,        trans_msa_3r,    gen_helper_msa_bset);
+TRANS_DF_E(BNEG,        trans_msa_3r,    gen_helper_msa_bneg);
 TRANS_DF_E(BINSL,       trans_msa_3r,    gen_helper_msa_binsl);
 TRANS_DF_E(BINSR,       trans_msa_3r,    gen_helper_msa_binsr);
 
+TRANS_DF_E(ADDV,        trans_msa_3r,    gen_helper_msa_addv);
+TRANS_DF_E(SUBV,        trans_msa_3r,    gen_helper_msa_subv);
+TRANS_DF_E(MAX_S,       trans_msa_3r,    gen_helper_msa_max_s);
+TRANS_DF_E(MAX_U,       trans_msa_3r,    gen_helper_msa_max_u);
+TRANS_DF_E(MIN_S,       trans_msa_3r,    gen_helper_msa_min_s);
+TRANS_DF_E(MIN_U,       trans_msa_3r,    gen_helper_msa_min_u);
+TRANS_DF_E(MAX_A,       trans_msa_3r,    gen_helper_msa_max_a);
+TRANS_DF_E(MIN_A,       trans_msa_3r,    gen_helper_msa_min_a);
+
+TRANS_DF_E(CEQ,         trans_msa_3r,    gen_helper_msa_ceq);
+TRANS_DF_E(CLT_S,       trans_msa_3r,    gen_helper_msa_clt_s);
+TRANS_DF_E(CLT_U,       trans_msa_3r,    gen_helper_msa_clt_u);
+TRANS_DF_E(CLE_S,       trans_msa_3r,    gen_helper_msa_cle_s);
+TRANS_DF_E(CLE_U,       trans_msa_3r,    gen_helper_msa_cle_u);
+
+TRANS_DF_E(ADD_A,       trans_msa_3r,    gen_helper_msa_add_a);
+TRANS_DF_E(ADDS_A,      trans_msa_3r,    gen_helper_msa_adds_a);
+TRANS_DF_E(ADDS_S,      trans_msa_3r,    gen_helper_msa_adds_s);
+TRANS_DF_E(ADDS_U,      trans_msa_3r,    gen_helper_msa_adds_u);
+TRANS_DF_E(AVE_S,       trans_msa_3r,    gen_helper_msa_ave_s);
+TRANS_DF_E(AVE_U,       trans_msa_3r,    gen_helper_msa_ave_u);
+TRANS_DF_E(AVER_S,      trans_msa_3r,    gen_helper_msa_aver_s);
+TRANS_DF_E(AVER_U,      trans_msa_3r,    gen_helper_msa_aver_u);
+
+TRANS_DF_E(SUBS_S,      trans_msa_3r,    gen_helper_msa_subs_s);
+TRANS_DF_E(SUBS_U,      trans_msa_3r,    gen_helper_msa_subs_u);
+TRANS_DF_E(SUBSUS_U,    trans_msa_3r,    gen_helper_msa_subsus_u);
+TRANS_DF_E(SUBSUU_S,    trans_msa_3r,    gen_helper_msa_subsuu_s);
+TRANS_DF_E(ASUB_S,      trans_msa_3r,    gen_helper_msa_asub_s);
+TRANS_DF_E(ASUB_U,      trans_msa_3r,    gen_helper_msa_asub_u);
+
+TRANS_DF_E(MULV,        trans_msa_3r,    gen_helper_msa_mulv);
+TRANS_DF_E(MADDV,       trans_msa_3r,    gen_helper_msa_maddv);
+TRANS_DF_E(MSUBV,       trans_msa_3r,    gen_helper_msa_msubv);
+TRANS_DF_E(DIV_S,       trans_msa_3r,    gen_helper_msa_div_s);
+TRANS_DF_E(DIV_U,       trans_msa_3r,    gen_helper_msa_div_u);
+TRANS_DF_E(MOD_S,       trans_msa_3r,    gen_helper_msa_mod_s);
+TRANS_DF_E(MOD_U,       trans_msa_3r,    gen_helper_msa_mod_u);
+
 TRANS_DF_B(DOTP_S,      trans_msa_3r,    gen_helper_msa_dotp_s);
 TRANS_DF_B(DOTP_U,      trans_msa_3r,    gen_helper_msa_dotp_u);
 TRANS_DF_B(DPADD_S,     trans_msa_3r,    gen_helper_msa_dpadd_s);
@@ -528,806 +514,21 @@ TRANS_DF_B(DPSUB_U,     trans_msa_3r,    gen_helper_msa_dpsub_u);
 
 TRANS_MSA(SLD,          trans_msa_3r_df, gen_helper_msa_sld_df);
 TRANS_MSA(SPLAT,        trans_msa_3r_df, gen_helper_msa_splat_df);
+TRANS_DF_E(PCKEV,       trans_msa_3r,    gen_helper_msa_pckev);
+TRANS_DF_E(PCKOD,       trans_msa_3r,    gen_helper_msa_pckod);
+TRANS_DF_E(ILVL,        trans_msa_3r,    gen_helper_msa_ilvl);
+TRANS_DF_E(ILVR,        trans_msa_3r,    gen_helper_msa_ilvr);
+TRANS_DF_E(ILVEV,       trans_msa_3r,    gen_helper_msa_ilvev);
+TRANS_DF_E(ILVOD,       trans_msa_3r,    gen_helper_msa_ilvod);
 
 TRANS_MSA(VSHF,         trans_msa_3r_df, gen_helper_msa_vshf_df);
+TRANS_DF_E(SRAR,        trans_msa_3r,    gen_helper_msa_srar);
+TRANS_DF_E(SRLR,        trans_msa_3r,    gen_helper_msa_srlr);
 TRANS_DF_B(HADD_S,      trans_msa_3r,    gen_helper_msa_hadd_s);
 TRANS_DF_B(HADD_U,      trans_msa_3r,    gen_helper_msa_hadd_u);
 TRANS_DF_B(HSUB_S,      trans_msa_3r,    gen_helper_msa_hsub_s);
 TRANS_DF_B(HSUB_U,      trans_msa_3r,    gen_helper_msa_hsub_u);
 
-static void gen_msa_3r(DisasContext *ctx)
-{
-#define MASK_MSA_3R(op)    (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
-    uint8_t df = (ctx->opcode >> 21) & 0x3;
-    uint8_t wt = (ctx->opcode >> 16) & 0x1f;
-    uint8_t ws = (ctx->opcode >> 11) & 0x1f;
-    uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-
-    TCGv_i32 tdf = tcg_const_i32(df);
-    TCGv_i32 twd = tcg_const_i32(wd);
-    TCGv_i32 tws = tcg_const_i32(ws);
-    TCGv_i32 twt = tcg_const_i32(wt);
-
-    switch (MASK_MSA_3R(ctx->opcode)) {
-    case OPC_BCLR_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_bclr_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_bclr_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_bclr_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_bclr_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_BNEG_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_bneg_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_bneg_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_bneg_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_bneg_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_BSET_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_bset_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_bset_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_bset_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_bset_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_ADD_A_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_add_a_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_add_a_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_add_a_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_add_a_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_ADDS_A_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_adds_a_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_adds_a_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_adds_a_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_adds_a_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_ADDS_S_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_adds_s_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_adds_s_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_adds_s_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_adds_s_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_ADDS_U_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_adds_u_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_adds_u_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_adds_u_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_adds_u_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_ADDV_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_addv_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_addv_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_addv_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_addv_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_AVE_S_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_ave_s_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_ave_s_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_ave_s_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_ave_s_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_AVE_U_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_ave_u_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_ave_u_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_ave_u_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_ave_u_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_AVER_S_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_aver_s_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_aver_s_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_aver_s_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_aver_s_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_AVER_U_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_aver_u_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_aver_u_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_aver_u_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_aver_u_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_CEQ_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_ceq_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_ceq_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_ceq_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_ceq_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_CLE_S_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_cle_s_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_cle_s_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_cle_s_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_cle_s_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_CLE_U_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_cle_u_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_cle_u_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_cle_u_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_cle_u_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_CLT_S_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_clt_s_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_clt_s_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_clt_s_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_clt_s_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_CLT_U_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_clt_u_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_clt_u_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_clt_u_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_clt_u_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_DIV_S_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_div_s_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_div_s_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_div_s_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_div_s_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_DIV_U_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_div_u_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_div_u_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_div_u_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_div_u_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_MAX_A_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_max_a_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_max_a_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_max_a_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_max_a_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_MAX_S_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_max_s_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_max_s_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_max_s_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_max_s_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_MAX_U_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_max_u_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_max_u_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_max_u_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_max_u_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_MIN_A_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_min_a_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_min_a_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_min_a_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_min_a_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_MIN_S_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_min_s_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_min_s_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_min_s_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_min_s_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_MIN_U_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_min_u_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_min_u_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_min_u_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_min_u_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_MOD_S_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_mod_s_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_mod_s_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_mod_s_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_mod_s_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_MOD_U_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_mod_u_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_mod_u_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_mod_u_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_mod_u_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_MADDV_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_maddv_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_maddv_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_maddv_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_maddv_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_MSUBV_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_msubv_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_msubv_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_msubv_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_msubv_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_ASUB_S_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_asub_s_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_asub_s_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_asub_s_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_asub_s_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_ASUB_U_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_asub_u_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_asub_u_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_asub_u_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_asub_u_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_ILVEV_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_ilvev_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_ilvev_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_ilvev_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_ilvev_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_ILVOD_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_ilvod_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_ilvod_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_ilvod_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_ilvod_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_ILVL_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_ilvl_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_ilvl_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_ilvl_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_ilvl_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_ILVR_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_ilvr_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_ilvr_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_ilvr_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_ilvr_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_PCKEV_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_pckev_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_pckev_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_pckev_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_pckev_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_PCKOD_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_pckod_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_pckod_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_pckod_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_pckod_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_SLL_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_sll_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_sll_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_sll_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_sll_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_SRA_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_sra_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_sra_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_sra_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_sra_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_SRAR_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_srar_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_srar_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_srar_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_srar_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_SRL_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_srl_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_srl_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_srl_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_srl_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_SRLR_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_srlr_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_srlr_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_srlr_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_srlr_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_SUBS_S_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_subs_s_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_subs_s_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_subs_s_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_subs_s_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_MULV_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_mulv_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_mulv_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_mulv_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_mulv_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_SUBV_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_subv_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_subv_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_subv_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_subv_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_SUBS_U_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_subs_u_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_subs_u_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_subs_u_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_subs_u_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_SUBSUS_U_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_subsus_u_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_subsus_u_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_subsus_u_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_subsus_u_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_SUBSUU_S_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_subsuu_s_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_subsuu_s_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_subsuu_s_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_subsuu_s_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    default:
-        MIPS_INVAL("MSA instruction");
-        gen_reserved_instruction(ctx);
-        break;
-    }
-    tcg_temp_free_i32(twd);
-    tcg_temp_free_i32(tws);
-    tcg_temp_free_i32(twt);
-    tcg_temp_free_i32(tdf);
-}
-
 static void gen_msa_elm_3e(DisasContext *ctx)
 {
 #define MASK_MSA_ELM_DF3E(op)   (MASK_MSA_MINOR(op) | (op & (0x3FF << 16)))
@@ -1684,17 +885,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
     }
 
     switch (MASK_MSA_MINOR(opcode)) {
-    case OPC_MSA_3R_0D:
-    case OPC_MSA_3R_0E:
-    case OPC_MSA_3R_0F:
-    case OPC_MSA_3R_10:
-    case OPC_MSA_3R_11:
-    case OPC_MSA_3R_12:
-    case OPC_MSA_3R_13:
-    case OPC_MSA_3R_14:
-    case OPC_MSA_3R_15:
-        gen_msa_3r(ctx);
-        break;
     case OPC_MSA_ELM:
         gen_msa_elm(ctx);
         break;
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 26/33] target/mips: Convert MSA ELM instruction format to decodetree
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (24 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 25/33] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-24 20:52   ` Richard Henderson
  2021-10-23 21:47 ` [PATCH 27/33] target/mips: Convert MSA COPY_U opcode " Philippe Mathieu-Daudé
                   ` (7 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Convert instructions with an immediate element index
and data format df/n to decodetree.

Since the 'data format' and 'n' fields are constant values,
use tcg_constant_i32() instead of a TCG temporaries.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      |  6 +++++
 target/mips/tcg/msa_translate.c | 46 +++++++++++++++++++++++----------
 2 files changed, 39 insertions(+), 13 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 3d0d9a52675..0f1674cd318 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -15,12 +15,14 @@
 
 &msa_r              df wd ws wt
 &msa_bz             df       wt sa
+&msa_elm            df wd ws
 &msa_ldst           df wd ws    sa
 
 @lsa                ...... rs:5 rt:5 rd:5 ... sa:2 ......   &r
 @ldst               ...... sa:s10 ws:5 wd:5 .... df:2       &msa_ldst
 @bz_v               ...... ... ..    wt:5 sa:16             &msa_bz df=3
 @bz                 ...... ...  df:2 wt:5 sa:16             &msa_bz
+@elm_df             ...... .... df:6      ws:5 wd:5 ......  &msa_elm
 @vec                ...... .....     wt:5 ws:5 wd:5 ......  &msa_r df=0
 @2r                 ...... ........  df:2 ws:5 wd:5 ......  &msa_r wt=0
 @2rf                ...... ......... df:1 ws:5 wd:5 ......  &msa_r wt=0
@@ -152,6 +154,10 @@ BNZ                 010001 111 .. ..... ................    @bz
   HSUB_S            011110 110.. ..... ..... .....  010101  @3r
   HSUB_U            011110 111.. ..... ..... .....  010101  @3r
 
+  SLDI              011110 0000 ...... ..... .....  011001  @elm_df
+  SPLATI            011110 0001 ...... ..... .....  011001  @elm_df
+  INSVE             011110 0101 ...... ..... .....  011001  @elm_df
+
   FCAF              011110 0000 . ..... ..... ..... 011010  @3rf
   FCUN              011110 0001 . ..... ..... ..... 011010  @3rf
   FCEQ              011110 0010 . ..... ..... ..... 011010  @3rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 7813c126069..95dcd4b5b06 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -29,15 +29,12 @@ enum {
 
 enum {
     /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
-    OPC_SLDI_df     = (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM,
     OPC_CTCMSA      = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
-    OPC_SPLATI_df   = (0x1 << 22) | (0x00 << 16) | OPC_MSA_ELM,
     OPC_CFCMSA      = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
     OPC_COPY_S_df   = (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM,
     OPC_MOVE_V      = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
     OPC_COPY_U_df   = (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM,
     OPC_INSERT_df   = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM,
-    OPC_INSVE_df    = (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM,
 };
 
 static const char msaregnames[][6] = {
@@ -561,6 +558,39 @@ static void gen_msa_elm_3e(DisasContext *ctx)
     tcg_temp_free_i32(tsr);
 }
 
+static bool trans_msa_elm_df(DisasContext *ctx, arg_msa_elm *a,
+                             void (*gen_msa_elm_df)(TCGv_ptr, TCGv_i32,
+                                                    TCGv_i32, TCGv_i32,
+                                                    TCGv_i32))
+{
+    TCGv_i32 twd;
+    TCGv_i32 tws;
+    TCGv_i32 tdf;
+    TCGv_i32 tn;
+    uint32_t df, n;
+
+    if (!df_extract(df_elm, a->df, &df, &n)) {
+        gen_reserved_instruction(ctx);
+        return true;
+    }
+
+    twd = tcg_const_i32(a->wd);
+    tws = tcg_const_i32(a->ws);
+    tdf = tcg_constant_i32(df);
+    tn = tcg_constant_i32(n);
+
+    gen_msa_elm_df(cpu_env, tdf, twd, tws, tn);
+
+    tcg_temp_free_i32(tws);
+    tcg_temp_free_i32(twd);
+
+    return true;
+}
+
+TRANS_MSA(SLDI,     trans_msa_elm_df, gen_helper_msa_sldi_df);
+TRANS_MSA(SPLATI,   trans_msa_elm_df, gen_helper_msa_splati_df);
+TRANS_MSA(INSVE,    trans_msa_elm_df, gen_helper_msa_insve_df);
+
 static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
 {
 #define MASK_MSA_ELM(op)    (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
@@ -570,18 +600,8 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
     TCGv_i32 tws = tcg_const_i32(ws);
     TCGv_i32 twd = tcg_const_i32(wd);
     TCGv_i32 tn  = tcg_const_i32(n);
-    TCGv_i32 tdf = tcg_constant_i32(df);
 
     switch (MASK_MSA_ELM(ctx->opcode)) {
-    case OPC_SLDI_df:
-        gen_helper_msa_sldi_df(cpu_env, tdf, twd, tws, tn);
-        break;
-    case OPC_SPLATI_df:
-        gen_helper_msa_splati_df(cpu_env, tdf, twd, tws, tn);
-        break;
-    case OPC_INSVE_df:
-        gen_helper_msa_insve_df(cpu_env, tdf, twd, tws, tn);
-        break;
     case OPC_COPY_S_df:
     case OPC_COPY_U_df:
     case OPC_INSERT_df:
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 27/33] target/mips: Convert MSA COPY_U opcode to decodetree
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (25 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 26/33] target/mips: Convert MSA ELM instruction format to decodetree Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-24 21:01   ` Richard Henderson
  2021-10-23 21:47 ` [PATCH 28/33] target/mips: Convert MSA COPY_S and INSERT opcodes " Philippe Mathieu-Daudé
                   ` (6 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Convert the COPY_U opcode (Element Copy to GPR Unsigned) to
decodetree.

Since the 'n' field is a constant value, use tcg_constant_i32()
instead of a TCG temporary.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      |  1 +
 target/mips/tcg/msa_translate.c | 90 +++++++++++++++++++++++----------
 2 files changed, 65 insertions(+), 26 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 0f1674cd318..80a06d12746 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -156,6 +156,7 @@ BNZ                 010001 111 .. ..... ................    @bz
 
   SLDI              011110 0000 ...... ..... .....  011001  @elm_df
   SPLATI            011110 0001 ...... ..... .....  011001  @elm_df
+  COPY_U            011110 0011 ...... ..... .....  011001  @elm_df
   INSVE             011110 0101 ...... ..... .....  011001  @elm_df
 
   FCAF              011110 0000 . ..... ..... ..... 011010  @3rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 95dcd4b5b06..e033b365fdd 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -33,7 +33,6 @@ enum {
     OPC_CFCMSA      = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
     OPC_COPY_S_df   = (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM,
     OPC_MOVE_V      = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
-    OPC_COPY_U_df   = (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM,
     OPC_INSERT_df   = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM,
 };
 
@@ -139,6 +138,11 @@ static inline bool check_msa_access(DisasContext *ctx)
         TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
                     NULL, gen_func##_h, gen_func##_w, gen_func##_d)
 
+#define TRANS_DF_W64(NAME, trans_func, gen_func) \
+        TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
+                    DF_HALF, DF_WORD, \
+                    gen_func##_b, gen_func##_h, gen_func##_w, NULL)
+
 static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
                                    TCGCond cond)
 {
@@ -591,6 +595,65 @@ TRANS_MSA(SLDI,     trans_msa_elm_df, gen_helper_msa_sldi_df);
 TRANS_MSA(SPLATI,   trans_msa_elm_df, gen_helper_msa_splati_df);
 TRANS_MSA(INSVE,    trans_msa_elm_df, gen_helper_msa_insve_df);
 
+static bool trans_msa_elm_d64(DisasContext *ctx, arg_msa_elm *a,
+                              enum CPUMIPSMSADataFormat df_max32,
+                              enum CPUMIPSMSADataFormat df_max64,
+                              void (*gen_msa_elm_b)(TCGv_ptr, TCGv_i32,
+                                                    TCGv_i32, TCGv_i32),
+                              void (*gen_msa_elm_h)(TCGv_ptr, TCGv_i32,
+                                                    TCGv_i32, TCGv_i32),
+                              void (*gen_msa_elm_w)(TCGv_ptr, TCGv_i32,
+                                                    TCGv_i32, TCGv_i32),
+                              void (*gen_msa_elm_d)(TCGv_ptr, TCGv_i32,
+                                                    TCGv_i32, TCGv_i32))
+{
+    TCGv_i32 twd;
+    TCGv_i32 tws;
+    TCGv_i32 tn;
+    uint32_t df, n;
+
+    if (!df_extract(df_elm, a->df, &df, &n)) {
+        gen_reserved_instruction(ctx);
+        return true;
+    }
+
+    if (df > (TARGET_LONG_BITS == 64 ? df_max64 : df_max32)) {
+        gen_reserved_instruction(ctx);
+        return true;
+    }
+
+    if (a->wd == 0) {
+        /* Treat as NOP. */
+        return true;
+    }
+
+    twd = tcg_const_i32(a->wd);
+    tws = tcg_const_i32(a->ws);
+    tn = tcg_constant_i32(n);
+
+    switch (a->df) {
+    case DF_BYTE:
+        gen_msa_elm_b(cpu_env, twd, tws, tn);
+        break;
+    case DF_HALF:
+        gen_msa_elm_h(cpu_env, twd, tws, tn);
+        break;
+    case DF_WORD:
+        gen_msa_elm_w(cpu_env, twd, tws, tn);
+        break;
+    case DF_DOUBLE:
+        g_assert_not_reached();
+        break;
+    }
+
+    tcg_temp_free_i32(tws);
+    tcg_temp_free_i32(twd);
+
+    return true;
+}
+
+TRANS_DF_W64(COPY_U,    trans_msa_elm_d64, gen_helper_msa_copy_u);
+
 static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
 {
 #define MASK_MSA_ELM(op)    (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
@@ -603,7 +666,6 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
 
     switch (MASK_MSA_ELM(ctx->opcode)) {
     case OPC_COPY_S_df:
-    case OPC_COPY_U_df:
     case OPC_INSERT_df:
 #if !defined(TARGET_MIPS64)
         /* Double format valid only for MIPS64 */
@@ -611,11 +673,6 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
             gen_reserved_instruction(ctx);
             break;
         }
-        if ((MASK_MSA_ELM(ctx->opcode) == OPC_COPY_U_df) &&
-              (df == DF_WORD)) {
-            gen_reserved_instruction(ctx);
-            break;
-        }
 #endif
         switch (MASK_MSA_ELM(ctx->opcode)) {
         case OPC_COPY_S_df:
@@ -634,25 +691,6 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
                 case DF_DOUBLE:
                     gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn);
                     break;
-#endif
-                default:
-                    assert(0);
-                }
-            }
-            break;
-        case OPC_COPY_U_df:
-            if (likely(wd != 0)) {
-                switch (df) {
-                case DF_BYTE:
-                    gen_helper_msa_copy_u_b(cpu_env, twd, tws, tn);
-                    break;
-                case DF_HALF:
-                    gen_helper_msa_copy_u_h(cpu_env, twd, tws, tn);
-                    break;
-#if defined(TARGET_MIPS64)
-                case DF_WORD:
-                    gen_helper_msa_copy_u_w(cpu_env, twd, tws, tn);
-                    break;
 #endif
                 default:
                     assert(0);
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 28/33] target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (26 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 27/33] target/mips: Convert MSA COPY_U opcode " Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-24 21:02   ` Richard Henderson
  2021-10-23 21:47 ` [PATCH 29/33] target/mips: Convert MSA MOVE.V opcode " Philippe Mathieu-Daudé
                   ` (5 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Convert the COPY_S (Element Copy to GPR Signed) opcode
and INSERT (GPR Insert Element) opcode to decodetree.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      |  2 +
 target/mips/tcg/msa_translate.c | 92 ++++-----------------------------
 2 files changed, 12 insertions(+), 82 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 80a06d12746..dc5e561b9dc 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -156,7 +156,9 @@ BNZ                 010001 111 .. ..... ................    @bz
 
   SLDI              011110 0000 ...... ..... .....  011001  @elm_df
   SPLATI            011110 0001 ...... ..... .....  011001  @elm_df
+  COPY_S            011110 0010 ...... ..... .....  011001  @elm_df
   COPY_U            011110 0011 ...... ..... .....  011001  @elm_df
+  INSERT            011110 0100 ...... ..... .....  011001  @elm_df
   INSVE             011110 0101 ...... ..... .....  011001  @elm_df
 
   FCAF              011110 0000 . ..... ..... ..... 011010  @3rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index e033b365fdd..ff5dbd99f84 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -31,9 +31,7 @@ enum {
     /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
     OPC_CTCMSA      = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
     OPC_CFCMSA      = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
-    OPC_COPY_S_df   = (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM,
     OPC_MOVE_V      = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
-    OPC_INSERT_df   = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM,
 };
 
 static const char msaregnames[][6] = {
@@ -138,6 +136,11 @@ static inline bool check_msa_access(DisasContext *ctx)
         TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
                     NULL, gen_func##_h, gen_func##_w, gen_func##_d)
 
+#define TRANS_DF_D64(NAME, trans_func, gen_func) \
+        TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
+                    DF_WORD, DF_DOUBLE, \
+                    gen_func##_b, gen_func##_h, gen_func##_w, gen_func##_d)
+
 #define TRANS_DF_W64(NAME, trans_func, gen_func) \
         TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
                     DF_HALF, DF_WORD, \
@@ -642,7 +645,8 @@ static bool trans_msa_elm_d64(DisasContext *ctx, arg_msa_elm *a,
         gen_msa_elm_w(cpu_env, twd, tws, tn);
         break;
     case DF_DOUBLE:
-        g_assert_not_reached();
+        assert(gen_msa_elm_d != NULL);
+        gen_msa_elm_d(cpu_env, twd, tws, tn);
         break;
     }
 
@@ -652,97 +656,21 @@ static bool trans_msa_elm_d64(DisasContext *ctx, arg_msa_elm *a,
     return true;
 }
 
+TRANS_DF_D64(COPY_S,    trans_msa_elm_d64, gen_helper_msa_copy_s);
 TRANS_DF_W64(COPY_U,    trans_msa_elm_d64, gen_helper_msa_copy_u);
-
-static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
-{
-#define MASK_MSA_ELM(op)    (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
-    uint8_t ws = (ctx->opcode >> 11) & 0x1f;
-    uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-
-    TCGv_i32 tws = tcg_const_i32(ws);
-    TCGv_i32 twd = tcg_const_i32(wd);
-    TCGv_i32 tn  = tcg_const_i32(n);
-
-    switch (MASK_MSA_ELM(ctx->opcode)) {
-    case OPC_COPY_S_df:
-    case OPC_INSERT_df:
-#if !defined(TARGET_MIPS64)
-        /* Double format valid only for MIPS64 */
-        if (df == DF_DOUBLE) {
-            gen_reserved_instruction(ctx);
-            break;
-        }
-#endif
-        switch (MASK_MSA_ELM(ctx->opcode)) {
-        case OPC_COPY_S_df:
-            if (likely(wd != 0)) {
-                switch (df) {
-                case DF_BYTE:
-                    gen_helper_msa_copy_s_b(cpu_env, twd, tws, tn);
-                    break;
-                case DF_HALF:
-                    gen_helper_msa_copy_s_h(cpu_env, twd, tws, tn);
-                    break;
-                case DF_WORD:
-                    gen_helper_msa_copy_s_w(cpu_env, twd, tws, tn);
-                    break;
-#if defined(TARGET_MIPS64)
-                case DF_DOUBLE:
-                    gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn);
-                    break;
-#endif
-                default:
-                    assert(0);
-                }
-            }
-            break;
-        case OPC_INSERT_df:
-            switch (df) {
-            case DF_BYTE:
-                gen_helper_msa_insert_b(cpu_env, twd, tws, tn);
-                break;
-            case DF_HALF:
-                gen_helper_msa_insert_h(cpu_env, twd, tws, tn);
-                break;
-            case DF_WORD:
-                gen_helper_msa_insert_w(cpu_env, twd, tws, tn);
-                break;
-#if defined(TARGET_MIPS64)
-            case DF_DOUBLE:
-                gen_helper_msa_insert_d(cpu_env, twd, tws, tn);
-                break;
-#endif
-            default:
-                assert(0);
-            }
-            break;
-        }
-        break;
-    default:
-        MIPS_INVAL("MSA instruction");
-        gen_reserved_instruction(ctx);
-    }
-    tcg_temp_free_i32(twd);
-    tcg_temp_free_i32(tws);
-    tcg_temp_free_i32(tn);
-}
+TRANS_DF_D64(INSERT,    trans_msa_elm_d64, gen_helper_msa_insert);
 
 static void gen_msa_elm(DisasContext *ctx)
 {
     uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
-    uint32_t df, n;
 
     if (dfn == 0x3E) {
         /* CTCMSA, CFCMSA, MOVE.V */
         gen_msa_elm_3e(ctx);
         return;
-    } else if (!df_extract(df_elm, dfn, &df, &n)) {
-        gen_reserved_instruction(ctx);
-        return;
     }
 
-    gen_msa_elm_df(ctx, df, n);
+    gen_reserved_instruction(ctx);
 }
 
 static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a,
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 29/33] target/mips: Convert MSA MOVE.V opcode to decodetree
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (27 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 28/33] target/mips: Convert MSA COPY_S and INSERT opcodes " Philippe Mathieu-Daudé
@ 2021-10-23 21:47 ` Philippe Mathieu-Daudé
  2021-10-24 21:09   ` Richard Henderson
  2021-10-23 21:48 ` [PATCH 30/33] target/mips: Convert CFCMSA and CTCMSA opcodes " Philippe Mathieu-Daudé
                   ` (4 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:47 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Convert the MOVE.V opcode (Vector Move) to decodetree.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      |  6 +++++-
 target/mips/tcg/msa_translate.c | 26 +++++++++++++++++++++-----
 2 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index dc5e561b9dc..1bde1983de3 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -23,6 +23,7 @@
 @bz_v               ...... ... ..    wt:5 sa:16             &msa_bz df=3
 @bz                 ...... ...  df:2 wt:5 sa:16             &msa_bz
 @elm_df             ...... .... df:6      ws:5 wd:5 ......  &msa_elm
+@elm                ...... ..........     ws:5 wd:5 ......  &msa_elm df=0
 @vec                ...... .....     wt:5 ws:5 wd:5 ......  &msa_r df=0
 @2r                 ...... ........  df:2 ws:5 wd:5 ......  &msa_r wt=0
 @2rf                ...... ......... df:1 ws:5 wd:5 ......  &msa_r wt=0
@@ -156,7 +157,10 @@ BNZ                 010001 111 .. ..... ................    @bz
 
   SLDI              011110 0000 ...... ..... .....  011001  @elm_df
   SPLATI            011110 0001 ...... ..... .....  011001  @elm_df
-  COPY_S            011110 0010 ...... ..... .....  011001  @elm_df
+  {
+    MOVE_V          011110 0010111110  ..... .....  011001  @elm
+    COPY_S          011110 0010 ...... ..... .....  011001  @elm_df
+  }
   COPY_U            011110 0011 ...... ..... .....  011001  @elm_df
   INSERT            011110 0100 ...... ..... .....  011001  @elm_df
   INSVE             011110 0101 ...... ..... .....  011001  @elm_df
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index ff5dbd99f84..b03cde964e0 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -31,7 +31,6 @@ enum {
     /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
     OPC_CTCMSA      = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
     OPC_CFCMSA      = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
-    OPC_MOVE_V      = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
 };
 
 static const char msaregnames[][6] = {
@@ -533,6 +532,26 @@ TRANS_DF_B(HADD_U,      trans_msa_3r,    gen_helper_msa_hadd_u);
 TRANS_DF_B(HSUB_S,      trans_msa_3r,    gen_helper_msa_hsub_s);
 TRANS_DF_B(HSUB_U,      trans_msa_3r,    gen_helper_msa_hsub_u);
 
+static bool trans_MOVE_V(DisasContext *ctx, arg_msa_elm *a)
+{
+    TCGv_i32 tsr;
+    TCGv_i32 tdt;
+
+    if (!check_msa_access(ctx)) {
+        return false;
+    }
+
+    tsr = tcg_const_i32(a->ws);
+    tdt = tcg_const_i32(a->wd);
+
+    gen_helper_msa_move_v(cpu_env, tdt, tsr);
+
+    tcg_temp_free_i32(tdt);
+    tcg_temp_free_i32(tsr);
+
+    return true;
+}
+
 static void gen_msa_elm_3e(DisasContext *ctx)
 {
 #define MASK_MSA_ELM_DF3E(op)   (MASK_MSA_MINOR(op) | (op & (0x3FF << 16)))
@@ -551,9 +570,6 @@ static void gen_msa_elm_3e(DisasContext *ctx)
         gen_helper_msa_cfcmsa(telm, cpu_env, tsr);
         gen_store_gpr(telm, dest);
         break;
-    case OPC_MOVE_V:
-        gen_helper_msa_move_v(cpu_env, tdt, tsr);
-        break;
     default:
         MIPS_INVAL("MSA instruction");
         gen_reserved_instruction(ctx);
@@ -665,7 +681,7 @@ static void gen_msa_elm(DisasContext *ctx)
     uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
 
     if (dfn == 0x3E) {
-        /* CTCMSA, CFCMSA, MOVE.V */
+        /* CTCMSA, CFCMSA */
         gen_msa_elm_3e(ctx);
         return;
     }
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 30/33] target/mips: Convert CFCMSA and CTCMSA opcodes to decodetree
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (28 preceding siblings ...)
  2021-10-23 21:47 ` [PATCH 29/33] target/mips: Convert MSA MOVE.V opcode " Philippe Mathieu-Daudé
@ 2021-10-23 21:48 ` Philippe Mathieu-Daudé
  2021-10-24 21:15   ` Richard Henderson
  2021-10-23 21:48 ` [PATCH 31/33] target/mips: Remove generic MSA opcode Philippe Mathieu-Daudé
                   ` (3 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:48 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Convert the CFCMSA (Copy From Control MSA register) and
CTCMSA (Copy To Control MSA register) opcodes to decodetree.

Since they respectively overlap with the SLDI and SPLATI
opcodes, use decodetree overlap groups.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      | 10 +++-
 target/mips/tcg/msa_translate.c | 95 ++++++++++++---------------------
 2 files changed, 42 insertions(+), 63 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 1bde1983de3..52dac0fde6d 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -155,8 +155,14 @@ BNZ                 010001 111 .. ..... ................    @bz
   HSUB_S            011110 110.. ..... ..... .....  010101  @3r
   HSUB_U            011110 111.. ..... ..... .....  010101  @3r
 
-  SLDI              011110 0000 ...... ..... .....  011001  @elm_df
-  SPLATI            011110 0001 ...... ..... .....  011001  @elm_df
+  {
+    CTCMSA          011110 0000111110  ..... .....  011001  @elm
+    SLDI            011110 0000 ...... ..... .....  011001  @elm_df
+  }
+  {
+    CFCMSA          011110 0001111110  ..... .....  011001  @elm
+    SPLATI          011110 0001 ...... ..... .....  011001  @elm_df
+  }
   {
     MOVE_V          011110 0010111110  ..... .....  011001  @elm
     COPY_S          011110 0010 ...... ..... .....  011001  @elm_df
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index b03cde964e0..51af6f39cc4 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -20,19 +20,6 @@
 /* Include the auto-generated decoder.  */
 #include "decode-msa.c.inc"
 
-#define OPC_MSA (0x1E << 26)
-
-#define MASK_MSA_MINOR(op)          (MASK_OP_MAJOR(op) | (op & 0x3F))
-enum {
-    OPC_MSA_ELM     = 0x19 | OPC_MSA,
-};
-
-enum {
-    /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
-    OPC_CTCMSA      = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
-    OPC_CFCMSA      = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
-};
-
 static const char msaregnames[][6] = {
     "w0.d0",  "w0.d1",  "w1.d0",  "w1.d1",
     "w2.d0",  "w2.d1",  "w3.d0",  "w3.d1",
@@ -552,33 +539,46 @@ static bool trans_MOVE_V(DisasContext *ctx, arg_msa_elm *a)
     return true;
 }
 
-static void gen_msa_elm_3e(DisasContext *ctx)
+static bool trans_CTCMSA(DisasContext *ctx, arg_msa_elm *a)
 {
-#define MASK_MSA_ELM_DF3E(op)   (MASK_MSA_MINOR(op) | (op & (0x3FF << 16)))
-    uint8_t source = (ctx->opcode >> 11) & 0x1f;
-    uint8_t dest = (ctx->opcode >> 6) & 0x1f;
-    TCGv telm = tcg_temp_new();
-    TCGv_i32 tsr = tcg_const_i32(source);
-    TCGv_i32 tdt = tcg_const_i32(dest);
+    TCGv telm;
+    TCGv_i32 tdt;
 
-    switch (MASK_MSA_ELM_DF3E(ctx->opcode)) {
-    case OPC_CTCMSA:
-        gen_load_gpr(telm, source);
-        gen_helper_msa_ctcmsa(cpu_env, telm, tdt);
-        break;
-    case OPC_CFCMSA:
-        gen_helper_msa_cfcmsa(telm, cpu_env, tsr);
-        gen_store_gpr(telm, dest);
-        break;
-    default:
-        MIPS_INVAL("MSA instruction");
-        gen_reserved_instruction(ctx);
-        break;
+    if (!check_msa_access(ctx)) {
+        return false;
     }
 
+    telm = tcg_temp_new();
+    tdt = tcg_const_i32(a->wd);
+
+    gen_load_gpr(telm, a->ws);
+    gen_helper_msa_ctcmsa(cpu_env, telm, tdt);
+
     tcg_temp_free(telm);
     tcg_temp_free_i32(tdt);
+
+    return true;
+}
+
+static bool trans_CFCMSA(DisasContext *ctx, arg_msa_elm *a)
+{
+    TCGv telm;
+    TCGv_i32 tsr;
+
+    if (!check_msa_access(ctx)) {
+        return false;
+    }
+
+    telm = tcg_temp_new();
+    tsr = tcg_const_i32(a->ws);
+
+    gen_helper_msa_cfcmsa(telm, cpu_env, tsr);
+    gen_store_gpr(telm, a->wd);
+
+    tcg_temp_free(telm);
     tcg_temp_free_i32(tsr);
+
+    return true;
 }
 
 static bool trans_msa_elm_df(DisasContext *ctx, arg_msa_elm *a,
@@ -676,19 +676,6 @@ TRANS_DF_D64(COPY_S,    trans_msa_elm_d64, gen_helper_msa_copy_s);
 TRANS_DF_W64(COPY_U,    trans_msa_elm_d64, gen_helper_msa_copy_u);
 TRANS_DF_D64(INSERT,    trans_msa_elm_d64, gen_helper_msa_insert);
 
-static void gen_msa_elm(DisasContext *ctx)
-{
-    uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
-
-    if (dfn == 0x3E) {
-        /* CTCMSA, CFCMSA */
-        gen_msa_elm_3e(ctx);
-        return;
-    }
-
-    gen_reserved_instruction(ctx);
-}
-
 static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a,
                           enum CPUMIPSMSADataFormat df_base,
                           void (*gen_msa_3rf)(TCGv_ptr, TCGv_i32, TCGv_i32,
@@ -880,21 +867,7 @@ TRANS_MSA(BSEL_V,   trans_msa_vec, gen_helper_msa_bsel_v);
 
 static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
 {
-    uint32_t opcode = ctx->opcode;
-
-    if (!check_msa_access(ctx)) {
-        return false;
-    }
-
-    switch (MASK_MSA_MINOR(opcode)) {
-    case OPC_MSA_ELM:
-        gen_msa_elm(ctx);
-        break;
-    default:
-        MIPS_INVAL("MSA instruction");
-        gen_reserved_instruction(ctx);
-        break;
-    }
+    gen_reserved_instruction(ctx);
 
     return true;
 }
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 31/33] target/mips: Remove generic MSA opcode
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (29 preceding siblings ...)
  2021-10-23 21:48 ` [PATCH 30/33] target/mips: Convert CFCMSA and CTCMSA opcodes " Philippe Mathieu-Daudé
@ 2021-10-23 21:48 ` Philippe Mathieu-Daudé
  2021-10-24 21:16   ` Richard Henderson
  2021-10-23 21:48 ` [PATCH 32/33] target/mips: Remove one MSA unnecessary decodetree overlap group Philippe Mathieu-Daudé
                   ` (2 subsequent siblings)
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:48 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

All opcodes have been converted to decodetree. The generic
MSA handler is now pointless, remove it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      | 2 --
 target/mips/tcg/msa_translate.c | 7 -------
 2 files changed, 9 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 52dac0fde6d..8189eae3499 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -245,6 +245,4 @@ BNZ                 010001 111 .. ..... ................    @bz
 
   LD                011110 .......... ..... .....   1000 .. @ldst
   ST                011110 .......... ..... .....   1001 .. @ldst
-
-  MSA               011110 --------------------------
 }
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 51af6f39cc4..5d8cad378e6 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -865,13 +865,6 @@ TRANS_MSA(BMNZ_V,   trans_msa_vec, gen_helper_msa_bmnz_v);
 TRANS_MSA(BMZ_V,    trans_msa_vec, gen_helper_msa_bmz_v);
 TRANS_MSA(BSEL_V,   trans_msa_vec, gen_helper_msa_bsel_v);
 
-static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
-{
-    gen_reserved_instruction(ctx);
-
-    return true;
-}
-
 static bool trans_msa_ldst(DisasContext *ctx, arg_msa_ldst *a,
                            void (*gen_msa_b)(TCGv_ptr, TCGv_i32, TCGv),
                            void (*gen_msa_h)(TCGv_ptr, TCGv_i32, TCGv),
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 32/33] target/mips: Remove one MSA unnecessary decodetree overlap group
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (30 preceding siblings ...)
  2021-10-23 21:48 ` [PATCH 31/33] target/mips: Remove generic MSA opcode Philippe Mathieu-Daudé
@ 2021-10-23 21:48 ` Philippe Mathieu-Daudé
  2021-10-24 21:17   ` Richard Henderson
  2021-10-23 21:48 ` [PATCH 33/33] target/mips: Adjust style in msa_translate_init() Philippe Mathieu-Daudé
  2021-10-24 18:26 ` [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Jiaxun Yang
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:48 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

Only the MSA generic opcode was overlapping with the other
instructions. Since the previous commit removed it, we can
now remove the overlap group. The decodetree script forces
us to re-indent the opcodes.

Diff trivial to review using `git-diff --ignore-all-space`.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode | 398 ++++++++++++++++++-------------------
 1 file changed, 198 insertions(+), 200 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 8189eae3499..9af995b71b6 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -44,205 +44,203 @@ BNZ_V               010001 01111  ..... ................    @bz_v
 BZ                  010001 110 .. ..... ................    @bz
 BNZ                 010001 111 .. ..... ................    @bz
 
+ANDI                011110 00 ........ ..... .....  000000  @i8
+ORI                 011110 01 ........ ..... .....  000000  @i8
+NORI                011110 10 ........ ..... .....  000000  @i8
+XORI                011110 11 ........ ..... .....  000000  @i8
+BMNZI               011110 00 ........ ..... .....  000001  @i8
+BMZI                011110 01 ........ ..... .....  000001  @i8
+BSELI               011110 10 ........ ..... .....  000001  @i8
+SHF                 011110 .. ........ ..... .....  000010  @i8_df
+
+ADDVI               011110 000 .. ..... ..... ..... 000110  @u5
+SUBVI               011110 001 .. ..... ..... ..... 000110  @u5
+MAXI_S              011110 010 .. ..... ..... ..... 000110  @s5
+MAXI_U              011110 011 .. ..... ..... ..... 000110  @u5
+MINI_S              011110 100 .. ..... ..... ..... 000110  @s5
+MINI_U              011110 101 .. ..... ..... ..... 000110  @u5
+
+CEQI                011110 000 .. ..... ..... ..... 000111  @s5
+CLTI_S              011110 010 .. ..... ..... ..... 000111  @s5
+CLTI_U              011110 011 .. ..... ..... ..... 000111  @u5
+CLEI_S              011110 100 .. ..... ..... ..... 000111  @s5
+CLEI_U              011110 101 .. ..... ..... ..... 000111  @u5
+
+LDI                 011110 110 .. ..........  ..... 000111  @ldi
+
+SLLI                011110 000 ....... ..... .....  001001  @bit
+SRAI                011110 001 ....... ..... .....  001001  @bit
+SRLI                011110 010 ....... ..... .....  001001  @bit
+BCLRI               011110 011 ....... ..... .....  001001  @bit
+BSETI               011110 100 ....... ..... .....  001001  @bit
+BNEGI               011110 101 ....... ..... .....  001001  @bit
+BINSLI              011110 110 ....... ..... .....  001001  @bit
+BINSRI              011110 111 ....... ..... .....  001001  @bit
+
+SAT_S               011110 000 ....... ..... .....  001010  @bit
+SAT_U               011110 001 ....... ..... .....  001010  @bit
+SRARI               011110 010 ....... ..... .....  001010  @bit
+SRLRI               011110 011 ....... ..... .....  001010  @bit
+
+SLL                 011110 000.. ..... ..... .....  001101  @3r
+SRA                 011110 001.. ..... ..... .....  001101  @3r
+SRL                 011110 010.. ..... ..... .....  001101  @3r
+BCLR                011110 011.. ..... ..... .....  001101  @3r
+BSET                011110 100.. ..... ..... .....  001101  @3r
+BNEG                011110 101.. ..... ..... .....  001101  @3r
+BINSL               011110 110.. ..... ..... .....  001101  @3r
+BINSR               011110 111.. ..... ..... .....  001101  @3r
+
+ADDV                011110 000.. ..... ..... .....  001110  @3r
+SUBV                011110 001.. ..... ..... .....  001110  @3r
+MAX_S               011110 010.. ..... ..... .....  001110  @3r
+MAX_U               011110 011.. ..... ..... .....  001110  @3r
+MIN_S               011110 100.. ..... ..... .....  001110  @3r
+MIN_U               011110 101.. ..... ..... .....  001110  @3r
+MAX_A               011110 110.. ..... ..... .....  001110  @3r
+MIN_A               011110 111.. ..... ..... .....  001110  @3r
+
+CEQ                 011110 000.. ..... ..... .....  001111  @3r
+CLT_S               011110 010.. ..... ..... .....  001111  @3r
+CLT_U               011110 011.. ..... ..... .....  001111  @3r
+CLE_S               011110 100.. ..... ..... .....  001111  @3r
+CLE_U               011110 101.. ..... ..... .....  001111  @3r
+
+ADD_A               011110 000.. ..... ..... .....  010000  @3r
+ADDS_A              011110 001.. ..... ..... .....  010000  @3r
+ADDS_S              011110 010.. ..... ..... .....  010000  @3r
+ADDS_U              011110 011.. ..... ..... .....  010000  @3r
+AVE_S               011110 100.. ..... ..... .....  010000  @3r
+AVE_U               011110 101.. ..... ..... .....  010000  @3r
+AVER_S              011110 110.. ..... ..... .....  010000  @3r
+AVER_U              011110 111.. ..... ..... .....  010000  @3r
+
+SUBS_S              011110 000.. ..... ..... .....  010001  @3r
+SUBS_U              011110 001.. ..... ..... .....  010001  @3r
+SUBSUS_U            011110 010.. ..... ..... .....  010001  @3r
+SUBSUU_S            011110 011.. ..... ..... .....  010001  @3r
+ASUB_S              011110 100.. ..... ..... .....  010001  @3r
+ASUB_U              011110 101.. ..... ..... .....  010001  @3r
+
+MULV                011110 000.. ..... ..... .....  010010  @3r
+MADDV               011110 001.. ..... ..... .....  010010  @3r
+MSUBV               011110 010.. ..... ..... .....  010010  @3r
+DIV_S               011110 100.. ..... ..... .....  010010  @3r
+DIV_U               011110 101.. ..... ..... .....  010010  @3r
+MOD_S               011110 110.. ..... ..... .....  010010  @3r
+MOD_U               011110 111.. ..... ..... .....  010010  @3r
+
+DOTP_S              011110 000.. ..... ..... .....  010011  @3r
+DOTP_U              011110 001.. ..... ..... .....  010011  @3r
+DPADD_S             011110 010.. ..... ..... .....  010011  @3r
+DPADD_U             011110 011.. ..... ..... .....  010011  @3r
+DPSUB_S             011110 100.. ..... ..... .....  010011  @3r
+DPSUB_U             011110 101.. ..... ..... .....  010011  @3r
+
+SLD                 011110 000 .. ..... ..... ..... 010100  @3r
+SPLAT               011110 001 .. ..... ..... ..... 010100  @3r
+PCKEV               011110 010 .. ..... ..... ..... 010100  @3r
+PCKOD               011110 011 .. ..... ..... ..... 010100  @3r
+ILVL                011110 100 .. ..... ..... ..... 010100  @3r
+ILVR                011110 101 .. ..... ..... ..... 010100  @3r
+ILVEV               011110 110 .. ..... ..... ..... 010100  @3r
+ILVOD               011110 111 .. ..... ..... ..... 010100  @3r
+
+VSHF                011110 000 .. ..... ..... ..... 010101  @3r
+SRAR                011110 001 .. ..... ..... ..... 010101  @3r
+SRLR                011110 010 .. ..... ..... ..... 010101  @3r
+HADD_S              011110 100.. ..... ..... .....  010101  @3r
+HADD_U              011110 101.. ..... ..... .....  010101  @3r
+HSUB_S              011110 110.. ..... ..... .....  010101  @3r
+HSUB_U              011110 111.. ..... ..... .....  010101  @3r
+
 {
-  ANDI              011110 00 ........ ..... .....  000000  @i8
-  ORI               011110 01 ........ ..... .....  000000  @i8
-  NORI              011110 10 ........ ..... .....  000000  @i8
-  XORI              011110 11 ........ ..... .....  000000  @i8
-  BMNZI             011110 00 ........ ..... .....  000001  @i8
-  BMZI              011110 01 ........ ..... .....  000001  @i8
-  BSELI             011110 10 ........ ..... .....  000001  @i8
-  SHF               011110 .. ........ ..... .....  000010  @i8_df
-
-  ADDVI             011110 000 .. ..... ..... ..... 000110  @u5
-  SUBVI             011110 001 .. ..... ..... ..... 000110  @u5
-  MAXI_S            011110 010 .. ..... ..... ..... 000110  @s5
-  MAXI_U            011110 011 .. ..... ..... ..... 000110  @u5
-  MINI_S            011110 100 .. ..... ..... ..... 000110  @s5
-  MINI_U            011110 101 .. ..... ..... ..... 000110  @u5
-
-  CEQI              011110 000 .. ..... ..... ..... 000111  @s5
-  CLTI_S            011110 010 .. ..... ..... ..... 000111  @s5
-  CLTI_U            011110 011 .. ..... ..... ..... 000111  @u5
-  CLEI_S            011110 100 .. ..... ..... ..... 000111  @s5
-  CLEI_U            011110 101 .. ..... ..... ..... 000111  @u5
-
-  LDI               011110 110 .. ..........  ..... 000111  @ldi
-
-  SLLI              011110 000 ....... ..... .....  001001  @bit
-  SRAI              011110 001 ....... ..... .....  001001  @bit
-  SRLI              011110 010 ....... ..... .....  001001  @bit
-  BCLRI             011110 011 ....... ..... .....  001001  @bit
-  BSETI             011110 100 ....... ..... .....  001001  @bit
-  BNEGI             011110 101 ....... ..... .....  001001  @bit
-  BINSLI            011110 110 ....... ..... .....  001001  @bit
-  BINSRI            011110 111 ....... ..... .....  001001  @bit
-
-  SAT_S             011110 000 ....... ..... .....  001010  @bit
-  SAT_U             011110 001 ....... ..... .....  001010  @bit
-  SRARI             011110 010 ....... ..... .....  001010  @bit
-  SRLRI             011110 011 ....... ..... .....  001010  @bit
-
-  SLL               011110 000.. ..... ..... .....  001101  @3r
-  SRA               011110 001.. ..... ..... .....  001101  @3r
-  SRL               011110 010.. ..... ..... .....  001101  @3r
-  BCLR              011110 011.. ..... ..... .....  001101  @3r
-  BSET              011110 100.. ..... ..... .....  001101  @3r
-  BNEG              011110 101.. ..... ..... .....  001101  @3r
-  BINSL             011110 110.. ..... ..... .....  001101  @3r
-  BINSR             011110 111.. ..... ..... .....  001101  @3r
-
-  ADDV              011110 000.. ..... ..... .....  001110  @3r
-  SUBV              011110 001.. ..... ..... .....  001110  @3r
-  MAX_S             011110 010.. ..... ..... .....  001110  @3r
-  MAX_U             011110 011.. ..... ..... .....  001110  @3r
-  MIN_S             011110 100.. ..... ..... .....  001110  @3r
-  MIN_U             011110 101.. ..... ..... .....  001110  @3r
-  MAX_A             011110 110.. ..... ..... .....  001110  @3r
-  MIN_A             011110 111.. ..... ..... .....  001110  @3r
-
-  CEQ               011110 000.. ..... ..... .....  001111  @3r
-  CLT_S             011110 010.. ..... ..... .....  001111  @3r
-  CLT_U             011110 011.. ..... ..... .....  001111  @3r
-  CLE_S             011110 100.. ..... ..... .....  001111  @3r
-  CLE_U             011110 101.. ..... ..... .....  001111  @3r
-
-  ADD_A             011110 000.. ..... ..... .....  010000  @3r
-  ADDS_A            011110 001.. ..... ..... .....  010000  @3r
-  ADDS_S            011110 010.. ..... ..... .....  010000  @3r
-  ADDS_U            011110 011.. ..... ..... .....  010000  @3r
-  AVE_S             011110 100.. ..... ..... .....  010000  @3r
-  AVE_U             011110 101.. ..... ..... .....  010000  @3r
-  AVER_S            011110 110.. ..... ..... .....  010000  @3r
-  AVER_U            011110 111.. ..... ..... .....  010000  @3r
-
-  SUBS_S            011110 000.. ..... ..... .....  010001  @3r
-  SUBS_U            011110 001.. ..... ..... .....  010001  @3r
-  SUBSUS_U          011110 010.. ..... ..... .....  010001  @3r
-  SUBSUU_S          011110 011.. ..... ..... .....  010001  @3r
-  ASUB_S            011110 100.. ..... ..... .....  010001  @3r
-  ASUB_U            011110 101.. ..... ..... .....  010001  @3r
-
-  MULV              011110 000.. ..... ..... .....  010010  @3r
-  MADDV             011110 001.. ..... ..... .....  010010  @3r
-  MSUBV             011110 010.. ..... ..... .....  010010  @3r
-  DIV_S             011110 100.. ..... ..... .....  010010  @3r
-  DIV_U             011110 101.. ..... ..... .....  010010  @3r
-  MOD_S             011110 110.. ..... ..... .....  010010  @3r
-  MOD_U             011110 111.. ..... ..... .....  010010  @3r
-
-  DOTP_S            011110 000.. ..... ..... .....  010011  @3r
-  DOTP_U            011110 001.. ..... ..... .....  010011  @3r
-  DPADD_S           011110 010.. ..... ..... .....  010011  @3r
-  DPADD_U           011110 011.. ..... ..... .....  010011  @3r
-  DPSUB_S           011110 100.. ..... ..... .....  010011  @3r
-  DPSUB_U           011110 101.. ..... ..... .....  010011  @3r
-
-  SLD               011110 000 .. ..... ..... ..... 010100  @3r
-  SPLAT             011110 001 .. ..... ..... ..... 010100  @3r
-  PCKEV             011110 010 .. ..... ..... ..... 010100  @3r
-  PCKOD             011110 011 .. ..... ..... ..... 010100  @3r
-  ILVL              011110 100 .. ..... ..... ..... 010100  @3r
-  ILVR              011110 101 .. ..... ..... ..... 010100  @3r
-  ILVEV             011110 110 .. ..... ..... ..... 010100  @3r
-  ILVOD             011110 111 .. ..... ..... ..... 010100  @3r
-
-  VSHF              011110 000 .. ..... ..... ..... 010101  @3r
-  SRAR              011110 001 .. ..... ..... ..... 010101  @3r
-  SRLR              011110 010 .. ..... ..... ..... 010101  @3r
-  HADD_S            011110 100.. ..... ..... .....  010101  @3r
-  HADD_U            011110 101.. ..... ..... .....  010101  @3r
-  HSUB_S            011110 110.. ..... ..... .....  010101  @3r
-  HSUB_U            011110 111.. ..... ..... .....  010101  @3r
-
-  {
-    CTCMSA          011110 0000111110  ..... .....  011001  @elm
-    SLDI            011110 0000 ...... ..... .....  011001  @elm_df
-  }
-  {
-    CFCMSA          011110 0001111110  ..... .....  011001  @elm
-    SPLATI          011110 0001 ...... ..... .....  011001  @elm_df
-  }
-  {
-    MOVE_V          011110 0010111110  ..... .....  011001  @elm
-    COPY_S          011110 0010 ...... ..... .....  011001  @elm_df
-  }
-  COPY_U            011110 0011 ...... ..... .....  011001  @elm_df
-  INSERT            011110 0100 ...... ..... .....  011001  @elm_df
-  INSVE             011110 0101 ...... ..... .....  011001  @elm_df
-
-  FCAF              011110 0000 . ..... ..... ..... 011010  @3rf
-  FCUN              011110 0001 . ..... ..... ..... 011010  @3rf
-  FCEQ              011110 0010 . ..... ..... ..... 011010  @3rf
-  FCUEQ             011110 0011 . ..... ..... ..... 011010  @3rf
-  FCLT              011110 0100 . ..... ..... ..... 011010  @3rf
-  FCULT             011110 0101 . ..... ..... ..... 011010  @3rf
-  FCLE              011110 0110 . ..... ..... ..... 011010  @3rf
-  FCULE             011110 0111 . ..... ..... ..... 011010  @3rf
-  FSAF              011110 1000 . ..... ..... ..... 011010  @3rf
-  FSUN              011110 1001 . ..... ..... ..... 011010  @3rf
-  FSEQ              011110 1010 . ..... ..... ..... 011010  @3rf
-  FSUEQ             011110 1011 . ..... ..... ..... 011010  @3rf
-  FSLT              011110 1100 . ..... ..... ..... 011010  @3rf
-  FSULT             011110 1101 . ..... ..... ..... 011010  @3rf
-  FSLE              011110 1110 . ..... ..... ..... 011010  @3rf
-  FSULE             011110 1111 . ..... ..... ..... 011010  @3rf
-
-  FADD              011110 0000 . ..... ..... ..... 011011  @3rf
-  FSUB              011110 0001 . ..... ..... ..... 011011  @3rf
-  FMUL              011110 0010 . ..... ..... ..... 011011  @3rf
-  FDIV              011110 0011 . ..... ..... ..... 011011  @3rf
-  FMADD             011110 0100 . ..... ..... ..... 011011  @3rf
-  FMSUB             011110 0101 . ..... ..... ..... 011011  @3rf
-  FEXP2             011110 0111 . ..... ..... ..... 011011  @3rf
-  FEXDO             011110 1000 . ..... ..... ..... 011011  @3rf
-  FTQ               011110 1010 . ..... ..... ..... 011011  @3rf
-  FMIN              011110 1100 . ..... ..... ..... 011011  @3rf
-  FMIN_A            011110 1101 . ..... ..... ..... 011011  @3rf
-  FMAX              011110 1110 . ..... ..... ..... 011011  @3rf
-  FMAX_A            011110 1111 . ..... ..... ..... 011011  @3rf
-
-  FCOR              011110 0001 . ..... ..... ..... 011100  @3rf
-  FCUNE             011110 0010 . ..... ..... ..... 011100  @3rf
-  FCNE              011110 0011 . ..... ..... ..... 011100  @3rf
-  MUL_Q             011110 0100 . ..... ..... ..... 011100  @3rf
-  MADD_Q            011110 0101 . ..... ..... ..... 011100  @3rf
-  MSUB_Q            011110 0110 . ..... ..... ..... 011100  @3rf
-  FSOR              011110 1001 . ..... ..... ..... 011100  @3rf
-  FSUNE             011110 1010 . ..... ..... ..... 011100  @3rf
-  FSNE              011110 1011 . ..... ..... ..... 011100  @3rf
-  MULR_Q            011110 1100 . ..... ..... ..... 011100  @3rf
-  MADDR_Q           011110 1101 . ..... ..... ..... 011100  @3rf
-  MSUBR_Q           011110 1110 . ..... ..... ..... 011100  @3rf
-
-  AND_V             011110 00000 ..... ..... .....  011110  @vec
-  OR_V              011110 00001 ..... ..... .....  011110  @vec
-  NOR_V             011110 00010 ..... ..... .....  011110  @vec
-  XOR_V             011110 00011 ..... ..... .....  011110  @vec
-  BMNZ_V            011110 00100 ..... ..... .....  011110  @vec
-  BMZ_V             011110 00101 ..... ..... .....  011110  @vec
-  BSEL_V            011110 00110 ..... ..... .....  011110  @vec
-  FILL              011110 11000000 .. ..... .....  011110  @2r
-  PCNT              011110 11000001 .. ..... .....  011110  @2r
-  NLOC              011110 11000010 .. ..... .....  011110  @2r
-  NLZC              011110 11000011 .. ..... .....  011110  @2r
-  FCLASS            011110 110010000 . ..... .....  011110  @2rf
-  FTRUNC_S          011110 110010001 . ..... .....  011110  @2rf
-  FTRUNC_U          011110 110010010 . ..... .....  011110  @2rf
-  FSQRT             011110 110010011 . ..... .....  011110  @2rf
-  FRSQRT            011110 110010100 . ..... .....  011110  @2rf
-  FRCP              011110 110010101 . ..... .....  011110  @2rf
-  FRINT             011110 110010110 . ..... .....  011110  @2rf
-  FLOG2             011110 110010111 . ..... .....  011110  @2rf
-  FEXUPL            011110 110011000 . ..... .....  011110  @2rf
-  FEXUPR            011110 110011001 . ..... .....  011110  @2rf
-  FFQL              011110 110011010 . ..... .....  011110  @2rf
-  FFQR              011110 110011011 . ..... .....  011110  @2rf
-  FTINT_S           011110 110011100 . ..... .....  011110  @2rf
-  FTINT_U           011110 110011101 . ..... .....  011110  @2rf
-  FFINT_S           011110 110011110 . ..... .....  011110  @2rf
-  FFINT_U           011110 110011111 . ..... .....  011110  @2rf
-
-  LD                011110 .......... ..... .....   1000 .. @ldst
-  ST                011110 .......... ..... .....   1001 .. @ldst
+  CTCMSA            011110 0000111110  ..... .....  011001  @elm
+  SLDI              011110 0000 ...... ..... .....  011001  @elm_df
 }
+{
+  CFCMSA            011110 0001111110  ..... .....  011001  @elm
+  SPLATI            011110 0001 ...... ..... .....  011001  @elm_df
+}
+{
+  MOVE_V            011110 0010111110  ..... .....  011001  @elm
+  COPY_S            011110 0010 ...... ..... .....  011001  @elm_df
+}
+COPY_U              011110 0011 ...... ..... .....  011001  @elm_df
+INSERT              011110 0100 ...... ..... .....  011001  @elm_df
+INSVE               011110 0101 ...... ..... .....  011001  @elm_df
+
+FCAF                011110 0000 . ..... ..... ..... 011010  @3rf
+FCUN                011110 0001 . ..... ..... ..... 011010  @3rf
+FCEQ                011110 0010 . ..... ..... ..... 011010  @3rf
+FCUEQ               011110 0011 . ..... ..... ..... 011010  @3rf
+FCLT                011110 0100 . ..... ..... ..... 011010  @3rf
+FCULT               011110 0101 . ..... ..... ..... 011010  @3rf
+FCLE                011110 0110 . ..... ..... ..... 011010  @3rf
+FCULE               011110 0111 . ..... ..... ..... 011010  @3rf
+FSAF                011110 1000 . ..... ..... ..... 011010  @3rf
+FSUN                011110 1001 . ..... ..... ..... 011010  @3rf
+FSEQ                011110 1010 . ..... ..... ..... 011010  @3rf
+FSUEQ               011110 1011 . ..... ..... ..... 011010  @3rf
+FSLT                011110 1100 . ..... ..... ..... 011010  @3rf
+FSULT               011110 1101 . ..... ..... ..... 011010  @3rf
+FSLE                011110 1110 . ..... ..... ..... 011010  @3rf
+FSULE               011110 1111 . ..... ..... ..... 011010  @3rf
+
+FADD                011110 0000 . ..... ..... ..... 011011  @3rf
+FSUB                011110 0001 . ..... ..... ..... 011011  @3rf
+FMUL                011110 0010 . ..... ..... ..... 011011  @3rf
+FDIV                011110 0011 . ..... ..... ..... 011011  @3rf
+FMADD               011110 0100 . ..... ..... ..... 011011  @3rf
+FMSUB               011110 0101 . ..... ..... ..... 011011  @3rf
+FEXP2               011110 0111 . ..... ..... ..... 011011  @3rf
+FEXDO               011110 1000 . ..... ..... ..... 011011  @3rf
+FTQ                 011110 1010 . ..... ..... ..... 011011  @3rf
+FMIN                011110 1100 . ..... ..... ..... 011011  @3rf
+FMIN_A              011110 1101 . ..... ..... ..... 011011  @3rf
+FMAX                011110 1110 . ..... ..... ..... 011011  @3rf
+FMAX_A              011110 1111 . ..... ..... ..... 011011  @3rf
+
+FCOR                011110 0001 . ..... ..... ..... 011100  @3rf
+FCUNE               011110 0010 . ..... ..... ..... 011100  @3rf
+FCNE                011110 0011 . ..... ..... ..... 011100  @3rf
+MUL_Q               011110 0100 . ..... ..... ..... 011100  @3rf
+MADD_Q              011110 0101 . ..... ..... ..... 011100  @3rf
+MSUB_Q              011110 0110 . ..... ..... ..... 011100  @3rf
+FSOR                011110 1001 . ..... ..... ..... 011100  @3rf
+FSUNE               011110 1010 . ..... ..... ..... 011100  @3rf
+FSNE                011110 1011 . ..... ..... ..... 011100  @3rf
+MULR_Q              011110 1100 . ..... ..... ..... 011100  @3rf
+MADDR_Q             011110 1101 . ..... ..... ..... 011100  @3rf
+MSUBR_Q             011110 1110 . ..... ..... ..... 011100  @3rf
+
+AND_V               011110 00000 ..... ..... .....  011110  @vec
+OR_V                011110 00001 ..... ..... .....  011110  @vec
+NOR_V               011110 00010 ..... ..... .....  011110  @vec
+XOR_V               011110 00011 ..... ..... .....  011110  @vec
+BMNZ_V              011110 00100 ..... ..... .....  011110  @vec
+BMZ_V               011110 00101 ..... ..... .....  011110  @vec
+BSEL_V              011110 00110 ..... ..... .....  011110  @vec
+FILL                011110 11000000 .. ..... .....  011110  @2r
+PCNT                011110 11000001 .. ..... .....  011110  @2r
+NLOC                011110 11000010 .. ..... .....  011110  @2r
+NLZC                011110 11000011 .. ..... .....  011110  @2r
+FCLASS              011110 110010000 . ..... .....  011110  @2rf
+FTRUNC_S            011110 110010001 . ..... .....  011110  @2rf
+FTRUNC_U            011110 110010010 . ..... .....  011110  @2rf
+FSQRT               011110 110010011 . ..... .....  011110  @2rf
+FRSQRT              011110 110010100 . ..... .....  011110  @2rf
+FRCP                011110 110010101 . ..... .....  011110  @2rf
+FRINT               011110 110010110 . ..... .....  011110  @2rf
+FLOG2               011110 110010111 . ..... .....  011110  @2rf
+FEXUPL              011110 110011000 . ..... .....  011110  @2rf
+FEXUPR              011110 110011001 . ..... .....  011110  @2rf
+FFQL                011110 110011010 . ..... .....  011110  @2rf
+FFQR                011110 110011011 . ..... .....  011110  @2rf
+FTINT_S             011110 110011100 . ..... .....  011110  @2rf
+FTINT_U             011110 110011101 . ..... .....  011110  @2rf
+FFINT_S             011110 110011110 . ..... .....  011110  @2rf
+FFINT_U             011110 110011111 . ..... .....  011110  @2rf
+
+LD                  011110 .......... ..... .....   1000 .. @ldst
+ST                  011110 .......... ..... .....   1001 .. @ldst
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* [PATCH 33/33] target/mips: Adjust style in msa_translate_init()
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (31 preceding siblings ...)
  2021-10-23 21:48 ` [PATCH 32/33] target/mips: Remove one MSA unnecessary decodetree overlap group Philippe Mathieu-Daudé
@ 2021-10-23 21:48 ` Philippe Mathieu-Daudé
  2021-10-24 21:18   ` Richard Henderson
  2021-10-24 18:26 ` [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Jiaxun Yang
  33 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-23 21:48 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Luis Pires, Richard Henderson,
	Philippe Mathieu-Daudé

While the first 'off' variable assignment is unused, it helps
to better understand the code logic. Move the assignation where
it would have been used so it is easier to compare the MSA
registers based on FPU ones versus the MSA specific registers.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa_translate.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 5d8cad378e6..d196cad196b 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -80,13 +80,15 @@ void msa_translate_init(void)
     int i;
 
     for (i = 0; i < 32; i++) {
-        int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
+        int off;
 
         /*
          * The MSA vector registers are mapped on the
          * scalar floating-point unit (FPU) registers.
          */
+        off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
         msa_wr_d[i * 2] = fpu_f64[i];
+
         off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
         msa_wr_d[i * 2 + 1] =
                 tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]);
-- 
2.31.1



^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 01/33] tests/tcg: Fix some targets default cross compiler path
  2021-10-23 21:47 ` [PATCH 01/33] tests/tcg: Fix some targets default cross compiler path Philippe Mathieu-Daudé
@ 2021-10-23 23:24   ` Richard Henderson
  0 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2021-10-23 23:24 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> We do not want a shell command substitution, but a parameter
> substitution (with assignment). Replace $() -> ${}, otherwise
> the expanded command return an empty string and the $cross_cc
> variable is not set.
> 
> Fixes: 634ef789f8e ("tests/tcg: add more default compilers to configure.sh")
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   tests/tcg/configure.sh | 14 +++++++-------
>   1 file changed, 7 insertions(+), 7 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 05/33] target/mips: Have check_msa_access() return a boolean
  2021-10-23 21:47 ` [PATCH 05/33] target/mips: Have check_msa_access() return a boolean Philippe Mathieu-Daudé
@ 2021-10-24  1:02   ` Richard Henderson
  2021-10-24 12:48     ` Philippe Mathieu-Daudé
  0 siblings, 1 reply; 78+ messages in thread
From: Richard Henderson @ 2021-10-24  1:02 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> Have check_msa_access() return a boolean value so we can
> return early if MSA is not enabled.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>   target/mips/tcg/msa_translate.c | 20 +++++++++++++-------
>   1 file changed, 13 insertions(+), 7 deletions(-)
> 
> diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
> index 3ef912da6b8..9e0a08fe335 100644
> --- a/target/mips/tcg/msa_translate.c
> +++ b/target/mips/tcg/msa_translate.c
> @@ -293,19 +293,19 @@ void msa_translate_init(void)
>       }
>   }
>   
> -static inline int check_msa_access(DisasContext *ctx)
> +static inline bool check_msa_access(DisasContext *ctx)
>   {
>       if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) &&
>                    !(ctx->hflags & MIPS_HFLAG_F64))) {
>           gen_reserved_instruction(ctx);
> -        return 0;
> +        return false;
>       }
>   
>       if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) {
>           generate_exception_end(ctx, EXCP_MSADIS);
> -        return 0;
> +        return false;
>       }

When we return false, we have raised an exception.

> @@ -354,7 +354,9 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond)
>   {
>       TCGv_i64 t0;
>   
> -    check_msa_access(ctx);
> +    if (!check_msa_access(ctx)) {
> +        return false;
> +    }

... which means that here we should return true, meaning that we have recognized the 
instruction and emitted some code for it.  In this case: we have recognized that the 
instruction is valid but not enabled.

Otherwise, we will return to decode_opc and (eventually) emit another 
gen_reserved_instruction.


r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 06/33] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum
  2021-10-23 21:47 ` [PATCH 06/33] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum Philippe Mathieu-Daudé
@ 2021-10-24  1:03   ` Richard Henderson
  0 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2021-10-24  1:03 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> Replace magic DataFormat value by the corresponding
> enum from CPUMIPSMSADataFormat.
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/tcg/msa_translate.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 07/33] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v
  2021-10-23 21:47 ` [PATCH 07/33] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v Philippe Mathieu-Daudé
@ 2021-10-24  1:05   ` Richard Henderson
  0 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2021-10-24  1:05 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> This 'shift amount' format is not always 16-bit, so name it
> generically as 'sa'. This will help to unify the various
> arg_msa decodetree generated structures.
> 
> Rename the @bz format -> @bz_v (specific @bz with df=3) and
> @bz_df -> @bz (generic @bz).
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>   target/mips/tcg/msa.decode      | 15 +++++++--------
>   target/mips/tcg/msa_translate.c | 20 ++++++++++----------
>   2 files changed, 17 insertions(+), 18 deletions(-)
> 
> diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
> index 74d99f6862c..aa784cf12a9 100644
> --- a/target/mips/tcg/msa.decode
> +++ b/target/mips/tcg/msa.decode
> @@ -13,19 +13,18 @@
>   
>   &r                  rs rt rd sa
>   
> -&msa_bz             df wt s16
> +&msa_bz             df       wt sa

Tab or odd spacing?  Otherwise,

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 08/33] target/mips: Convert MSA LDI opcode to decodetree
  2021-10-23 21:47 ` [PATCH 08/33] target/mips: Convert MSA LDI opcode to decodetree Philippe Mathieu-Daudé
@ 2021-10-24  1:53   ` Richard Henderson
  0 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2021-10-24  1:53 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> +static bool trans_LDI(DisasContext *ctx, arg_msa_ldst *a)
> +{
> +    TCGv_i32 tdf;
> +    TCGv_i32 twd;
> +    TCGv_i32 timm;
> +
> +    if (!check_msa_access(ctx)) {
> +        return false;
> +    }

Return true.  I won't mention the return after check_msa_access again.

> +    twd = tcg_const_i32(a->wd);
> +    timm = tcg_const_i32(a->sa);

tcg_constant_i32.


r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 09/33] target/mips: Introduce generic TRANS_CHECK() for decodetree helpers
  2021-10-23 21:47 ` [PATCH 09/33] target/mips: Introduce generic TRANS_CHECK() for decodetree helpers Philippe Mathieu-Daudé
@ 2021-10-24  1:58   ` Richard Henderson
  0 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2021-10-24  1:58 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> Similar to the TRANS() macro introduced in commit fb3164e412d,
> introduce TRANS_CHECK() which takes a boolean expression as
> argument.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>   target/mips/tcg/translate.h | 9 +++++++++
>   1 file changed, 9 insertions(+)
> 
> diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
> index 6111493651f..3ef09cc50c9 100644
> --- a/target/mips/tcg/translate.h
> +++ b/target/mips/tcg/translate.h
> @@ -224,6 +224,15 @@ bool decode_ext_vr54xx(DisasContext *ctx, uint32_t insn);
>       static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
>       { return FUNC(ctx, a, __VA_ARGS__); }
>   
> +#define TRANS_CHECK(NAME, CHECK_EXPR, FUNC, ...) \
> +    static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
> +    { \
> +        if (!(CHECK_EXPR)) { \
> +            return false; \
> +        } \
> +        return FUNC(ctx, a, __VA_ARGS__); \
> +    }

So... if you're going to do this generically, you may want to adjust check_msa_access. 
OTOH, perhaps all you want is a more local TRANS_MSA, with the CHECK_EXPR built in.


r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 11/33] target/mips: Convert MSA I5 instruction format to decodetree
  2021-10-23 21:47 ` [PATCH 11/33] target/mips: Convert MSA I5 instruction format to decodetree Philippe Mathieu-Daudé
@ 2021-10-24  2:10   ` Richard Henderson
  0 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2021-10-24  2:10 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> +static bool trans_msa_i5(DisasContext *ctx, arg_msa_ldst *a,
> +                         void (*gen_msa_i5)(TCGv_ptr, TCGv_i32, TCGv_i32,
> +                                            TCGv_i32, TCGv_i32))
>   {
> +    TCGv_i32 tdf = tcg_constant_i32(a->df);
> +    TCGv_i32 twd = tcg_const_i32(a->wd);
> +    TCGv_i32 tws = tcg_const_i32(a->ws);
> +    TCGv_i32 timm = tcg_const_i32(a->sa);

tcg_constant_i32.  Otherwise,

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 10/33] target/mips: Extract df_extract() helper
  2021-10-23 21:47 ` [PATCH 10/33] target/mips: Extract df_extract() helper Philippe Mathieu-Daudé
@ 2021-10-24  2:26   ` Richard Henderson
  0 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2021-10-24  2:26 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> Extract the common code which parses data formats to an helper.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>   target/mips/tcg/msa_translate.c | 68 +++++++++++++++++++--------------
>   1 file changed, 39 insertions(+), 29 deletions(-)
> 
> diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
> index 3b0dfcca69d..7c1bbfaec61 100644
> --- a/target/mips/tcg/msa_translate.c
> +++ b/target/mips/tcg/msa_translate.c
> @@ -272,6 +272,40 @@ static const char msaregnames[][6] = {
>       "w30.d0", "w30.d1", "w31.d0", "w31.d1",
>   };
>   
> +/* Encoding of Operation Field */
> +static const struct dfe {
> +    enum CPUMIPSMSADataFormat df;
> +    int start;
> +    int length;
> +    uint32_t value;
> +} df_elm[] = {
> +    /* Table 3.26 ELM Instruction Format */
> +    {DF_BYTE,   4, 2, 0b00},
> +    {DF_HALF,   3, 3, 0b100},
> +    {DF_WORD,   2, 4, 0b1100},
> +    {DF_DOUBLE, 1, 5, 0b11100}
> +}, df_bit[] = {
> +    /* Table 3.28 BIT Instruction Format */
> +    {DF_BYTE,   3, 4, 0b1110},
> +    {DF_HALF,   4, 3, 0b110},
> +    {DF_WORD,   5, 2, 0b10},
> +    {DF_DOUBLE, 6, 1, 0b0}
> +};

Possibly clearer as separate declarations instead of the comma.
The df field is redundant with the index.  At which point perhaps a

typedef const struct dfe dfe4[4];

might be helpful, both for the two declarations and...

> +/* Extract Operation Field (used by ELM & BIT instructions) */
> +static bool df_extract(const struct dfe *s, int value,
> +                       enum CPUMIPSMSADataFormat *df, uint32_t *x)

... the parameter.

> +    uint32_t df, m;
...
> +    if (!df_extract(df_bit, dfm, &df, &m)) {

How does the type of df not match the parameter?
Incomplete rebase?


r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 12/33] target/mips: Convert MSA BIT instruction format to decodetree
  2021-10-23 21:47 ` [PATCH 12/33] target/mips: Convert MSA BIT " Philippe Mathieu-Daudé
@ 2021-10-24  2:45   ` Richard Henderson
  0 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2021-10-24  2:45 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
>   @u5                 ...... ... df:2 sa:5  ws:5 wd:5 ......  &msa_ldst
>   @s5                 ...... ... df:2 sa:s5 ws:5 wd:5 ......  &msa_ldst
>   @ldi                ...... ... df:2 sa:s10     wd:5 ......  &msa_ldst ws=0
> +@bit                ...... ... df:7       ws:5 wd:5 ......  &msa_ldst sa=0

Not sure why you seem over-keen to use &msa_ldst, with fields that don't apply to these 
insns.  Drop that and you can more properly name the field dfm.

> +    twd = tcg_const_i32(a->wd);
> +    tws = tcg_const_i32(a->ws);

tcg_constant_i32.


r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 13/33] target/mips: Convert MSA SHF opcode to decodetree
  2021-10-23 21:47 ` [PATCH 13/33] target/mips: Convert MSA SHF opcode " Philippe Mathieu-Daudé
@ 2021-10-24  3:40   ` Richard Henderson
  0 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2021-10-24  3:40 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> +    twd = tcg_const_i32(a->wd);
> +    tws = tcg_const_i32(a->ws);
> +    timm = tcg_const_i32(a->sa);

tcg_constant_i32.  Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 14/33] target/mips: Convert MSA I8 instruction format to decodetree
  2021-10-23 21:47 ` [PATCH 14/33] target/mips: Convert MSA I8 instruction format " Philippe Mathieu-Daudé
@ 2021-10-24  3:45   ` Richard Henderson
  0 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2021-10-24  3:45 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> +    TCGv_i32 twd = tcg_const_i32(a->wd);
> +    TCGv_i32 tws = tcg_const_i32(a->ws);
> +    TCGv_i32 timm = tcg_const_i32(a->sa);

tcg_constant_i32.  Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 15/33] target/mips: Convert MSA load/store instruction format to decodetree
  2021-10-23 21:47 ` [PATCH 15/33] target/mips: Convert MSA load/store " Philippe Mathieu-Daudé
@ 2021-10-24  4:53   ` Richard Henderson
  2021-10-24 11:18     ` Philippe Mathieu-Daudé
  0 siblings, 1 reply; 78+ messages in thread
From: Richard Henderson @ 2021-10-24  4:53 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> +#define TRANS_DF_E(NAME, trans_func, gen_func) \
> +        TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
> +                    gen_func##_b, gen_func##_h, gen_func##_w, gen_func##_d)

I think this would be better as a table.

#define TRANS_DF_E(NAME, trans_func, gen_func) \
     static void (* const NAME##_tab[4])(TCGv_ptr, TCGv_i32, TCGV) = { \
         gen_func##_b, gen_func##_h, gen_func##_w, gen_func##_d)       \
     };                                                                \
     TRANS_MSA(trans_func, NAME##_tag[a->df])


r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 16/33] target/mips: Convert MSA 2RF instruction format to decodetree
  2021-10-23 21:47 ` [PATCH 16/33] target/mips: Convert MSA 2RF " Philippe Mathieu-Daudé
@ 2021-10-24  5:01   ` Richard Henderson
  0 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2021-10-24  5:01 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> +    TCGv_i32 twd = tcg_const_i32(a->wd);
> +    TCGv_i32 tws = tcg_const_i32(a->ws);

tcg_constant_i32.  Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 17/33] target/mips: Convert MSA FILL opcode to decodetree
  2021-10-23 21:47 ` [PATCH 17/33] target/mips: Convert MSA FILL opcode " Philippe Mathieu-Daudé
@ 2021-10-24  5:04   ` Richard Henderson
  2021-10-24 16:44     ` Philippe Mathieu-Daudé
  0 siblings, 1 reply; 78+ messages in thread
From: Richard Henderson @ 2021-10-24  5:04 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> Convert the FILL opcode (Vector Fill from GPR) to decodetree.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>   target/mips/tcg/msa.decode      |  2 ++
>   target/mips/tcg/msa_translate.c | 40 +++++++++++++++++++++++----------
>   2 files changed, 30 insertions(+), 12 deletions(-)
> 
> diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
> index 2997bfa24e3..e97490cf880 100644
> --- a/target/mips/tcg/msa.decode
> +++ b/target/mips/tcg/msa.decode
> @@ -21,6 +21,7 @@
>   @ldst               ...... sa:s10 ws:5 wd:5 .... df:2       &msa_ldst
>   @bz_v               ...... ... ..    wt:5 sa:16             &msa_bz df=3
>   @bz                 ...... ...  df:2 wt:5 sa:16             &msa_bz
> +@2r                 ...... ........  df:2 ws:5 wd:5 ......  &msa_r wt=0
>   @2rf                ...... ......... df:1 ws:5 wd:5 ......  &msa_r wt=0
>   @u5                 ...... ... df:2 sa:5  ws:5 wd:5 ......  &msa_ldst
>   @s5                 ...... ... df:2 sa:s5 ws:5 wd:5 ......  &msa_ldst
> @@ -76,6 +77,7 @@ BNZ                 010001 111 .. ..... ................    @bz
>     SRARI             011110 010 ....... ..... .....  001010  @bit
>     SRLRI             011110 011 ....... ..... .....  001010  @bit
>   
> +  FILL              011110 11000000 .. ..... .....  011110  @2r
>     FCLASS            011110 110010000 . ..... .....  011110  @2rf
>     FTRUNC_S          011110 110010001 . ..... .....  011110  @2rf
>     FTRUNC_U          011110 110010010 . ..... .....  011110  @2rf
> diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
> index c6a77381c0e..fc0b80f83ac 100644
> --- a/target/mips/tcg/msa_translate.c
> +++ b/target/mips/tcg/msa_translate.c
> @@ -53,7 +53,6 @@ enum {
>       OPC_MSA_2R      = (0x18 << 21) | OPC_MSA_VEC,
>   
>       /* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
> -    OPC_FILL_df     = (0x00 << 18) | OPC_MSA_2R,
>       OPC_PCNT_df     = (0x01 << 18) | OPC_MSA_2R,
>       OPC_NLOC_df     = (0x02 << 18) | OPC_MSA_2R,
>       OPC_NLZC_df     = (0x03 << 18) | OPC_MSA_2R,
> @@ -1844,17 +1843,6 @@ static void gen_msa_2r(DisasContext *ctx)
>       TCGv_i32 tws = tcg_const_i32(ws);
>   
>       switch (MASK_MSA_2R(ctx->opcode)) {
> -    case OPC_FILL_df:
> -#if !defined(TARGET_MIPS64)
> -        /* Double format valid only for MIPS64 */
> -        if (df == DF_DOUBLE) {
> -            gen_reserved_instruction(ctx);
> -            break;
> -        }
> -#endif
> -        gen_helper_msa_fill_df(cpu_env, tcg_constant_i32(df),
> -                               twd, tws); /* trs */
> -        break;
>       case OPC_NLOC_df:
>           switch (df) {
>           case DF_BYTE:
> @@ -1913,6 +1901,34 @@ static void gen_msa_2r(DisasContext *ctx)
>       tcg_temp_free_i32(tws);
>   }
>   
> +static bool trans_FILL(DisasContext *ctx, arg_msa_r *a)
> +{
> +    TCGv_i32 twd;
> +    TCGv_i32 tws;
> +    TCGv_i32 tdf;
> +
> +    if (!check_msa_access(ctx)) {
> +        return false;
> +    }
> +
> +    if (TARGET_LONG_BITS != 64 && a->df == DF_DOUBLE) {
> +        /* Double format valid only for MIPS64 */
> +        gen_reserved_instruction(ctx);
> +        return true;
> +    }

I expect this reserved check should be above the MSA is disabled check, within 
check_msa_access.

> +    twd = tcg_const_i32(a->wd);
> +    tws = tcg_const_i32(a->ws);

tcg_constant_i32.

r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 18/33] target/mips: Convert MSA 2R instruction format to decodetree
  2021-10-23 21:47 ` [PATCH 18/33] target/mips: Convert MSA 2R instruction format " Philippe Mathieu-Daudé
@ 2021-10-24  5:14   ` Richard Henderson
  0 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2021-10-24  5:14 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> +static bool trans_msa_2r(DisasContext *ctx, arg_msa_r *a,
> +                         void (*gen_msa_2r_b)(TCGv_ptr, TCGv_i32, TCGv_i32),
> +                         void (*gen_msa_2r_h)(TCGv_ptr, TCGv_i32, TCGv_i32),
> +                         void (*gen_msa_2r_w)(TCGv_ptr, TCGv_i32, TCGv_i32),
> +                         void (*gen_msa_2r_d)(TCGv_ptr, TCGv_i32, TCGv_i32))
>   {
> -#define MASK_MSA_2R(op)     (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
> -                            (op & (0x7 << 18)))
> -    uint8_t ws = (ctx->opcode >> 11) & 0x1f;
> -    uint8_t wd = (ctx->opcode >> 6) & 0x1f;
> -    uint8_t df = (ctx->opcode >> 16) & 0x3;
> -    TCGv_i32 twd = tcg_const_i32(wd);
> -    TCGv_i32 tws = tcg_const_i32(ws);
> +    TCGv_i32 twd = tcg_const_i32(a->wd);
> +    TCGv_i32 tws = tcg_const_i32(a->ws);

tcg_constant_i32.

Missing check_msa_access.

> +    switch (a->df) {
> +    case DF_BYTE:
> +        if (gen_msa_2r_b == NULL) {
> +            gen_reserved_instruction(ctx);
> +        } else {
> +            gen_msa_2r_b(cpu_env, twd, tws);

Why the null check?


r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 19/33] target/mips: Convert MSA VEC instruction format to decodetree
  2021-10-23 21:47 ` [PATCH 19/33] target/mips: Convert MSA VEC " Philippe Mathieu-Daudé
@ 2021-10-24  5:17   ` Richard Henderson
  0 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2021-10-24  5:17 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> +    TCGv_i32 twd = tcg_const_i32(a->wd);
> +    TCGv_i32 tws = tcg_const_i32(a->ws);
> +    TCGv_i32 twt = tcg_const_i32(a->wt);

tcg_constant_i32.  Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 15/33] target/mips: Convert MSA load/store instruction format to decodetree
  2021-10-24  4:53   ` Richard Henderson
@ 2021-10-24 11:18     ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-24 11:18 UTC (permalink / raw)
  To: Richard Henderson, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/24/21 06:53, Richard Henderson wrote:
> On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
>> +#define TRANS_DF_E(NAME, trans_func, gen_func) \
>> +        TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
>> +                    gen_func##_b, gen_func##_h, gen_func##_w,
>> gen_func##_d)
> 
> I think this would be better as a table.
> 
> #define TRANS_DF_E(NAME, trans_func, gen_func) \
>     static void (* const NAME##_tab[4])(TCGv_ptr, TCGv_i32, TCGV) = { \
>         gen_func##_b, gen_func##_h, gen_func##_w, gen_func##_d)       \
>     };                                                                \
>     TRANS_MSA(trans_func, NAME##_tag[a->df])

Nice tip! Thanks :>


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 05/33] target/mips: Have check_msa_access() return a boolean
  2021-10-24  1:02   ` Richard Henderson
@ 2021-10-24 12:48     ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-24 12:48 UTC (permalink / raw)
  To: Richard Henderson, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/24/21 03:02, Richard Henderson wrote:
> On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
>> Have check_msa_access() return a boolean value so we can
>> return early if MSA is not enabled.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>>   target/mips/tcg/msa_translate.c | 20 +++++++++++++-------
>>   1 file changed, 13 insertions(+), 7 deletions(-)
>>
>> diff --git a/target/mips/tcg/msa_translate.c
>> b/target/mips/tcg/msa_translate.c
>> index 3ef912da6b8..9e0a08fe335 100644
>> --- a/target/mips/tcg/msa_translate.c
>> +++ b/target/mips/tcg/msa_translate.c
>> @@ -293,19 +293,19 @@ void msa_translate_init(void)
>>       }
>>   }
>>   -static inline int check_msa_access(DisasContext *ctx)
>> +static inline bool check_msa_access(DisasContext *ctx)
>>   {
>>       if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) &&
>>                    !(ctx->hflags & MIPS_HFLAG_F64))) {
>>           gen_reserved_instruction(ctx);
>> -        return 0;
>> +        return false;
>>       }
>>         if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) {
>>           generate_exception_end(ctx, EXCP_MSADIS);
>> -        return 0;
>> +        return false;
>>       }
> 
> When we return false, we have raised an exception.
> 
>> @@ -354,7 +354,9 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int
>> wt, int s16, TCGCond cond)
>>   {
>>       TCGv_i64 t0;
>>   -    check_msa_access(ctx);
>> +    if (!check_msa_access(ctx)) {
>> +        return false;
>> +    }
> 
> ... which means that here we should return true, meaning that we have
> recognized the instruction and emitted some code for it.  In this case:
> we have recognized that the instruction is valid but not enabled.
> 
> Otherwise, we will return to decode_opc and (eventually) emit another
> gen_reserved_instruction.

Yes, this is what I intended to do. I incorrectly copied/pasted 'false'
then it spread all over the file. Thanks for catching this.


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 17/33] target/mips: Convert MSA FILL opcode to decodetree
  2021-10-24  5:04   ` Richard Henderson
@ 2021-10-24 16:44     ` Philippe Mathieu-Daudé
  2021-10-24 17:26       ` Richard Henderson
  0 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-24 16:44 UTC (permalink / raw)
  To: Richard Henderson, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/24/21 07:04, Richard Henderson wrote:
> On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
>> Convert the FILL opcode (Vector Fill from GPR) to decodetree.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>>   target/mips/tcg/msa.decode      |  2 ++
>>   target/mips/tcg/msa_translate.c | 40 +++++++++++++++++++++++----------
>>   2 files changed, 30 insertions(+), 12 deletions(-)

>>   +static bool trans_FILL(DisasContext *ctx, arg_msa_r *a)
>> +{
>> +    TCGv_i32 twd;
>> +    TCGv_i32 tws;
>> +    TCGv_i32 tdf;
>> +
>> +    if (!check_msa_access(ctx)) {
>> +        return false;
>> +    }
>> +
>> +    if (TARGET_LONG_BITS != 64 && a->df == DF_DOUBLE) {
>> +        /* Double format valid only for MIPS64 */
>> +        gen_reserved_instruction(ctx);
>> +        return true;
>> +    }
> 
> I expect this reserved check should be above the MSA is disabled check,
> within check_msa_access.
> 
>> +    twd = tcg_const_i32(a->wd);
>> +    tws = tcg_const_i32(a->ws);
> 
> tcg_constant_i32.

Hmm I am confused here, only 'df' is constant, 'ws' is GPR[$rs].
Since it is limited in [0,32[ and used read-only by the helper,
we can also pass it as constant?


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 17/33] target/mips: Convert MSA FILL opcode to decodetree
  2021-10-24 16:44     ` Philippe Mathieu-Daudé
@ 2021-10-24 17:26       ` Richard Henderson
  2021-10-25 16:43         ` Philippe Mathieu-Daudé
  0 siblings, 1 reply; 78+ messages in thread
From: Richard Henderson @ 2021-10-24 17:26 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/24/21 9:44 AM, Philippe Mathieu-Daudé wrote:
> On 10/24/21 07:04, Richard Henderson wrote:
>> On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
>>> Convert the FILL opcode (Vector Fill from GPR) to decodetree.
>>>
>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>> ---
>>>    target/mips/tcg/msa.decode      |  2 ++
>>>    target/mips/tcg/msa_translate.c | 40 +++++++++++++++++++++++----------
>>>    2 files changed, 30 insertions(+), 12 deletions(-)
> 
>>>    +static bool trans_FILL(DisasContext *ctx, arg_msa_r *a)
>>> +{
>>> +    TCGv_i32 twd;
>>> +    TCGv_i32 tws;
>>> +    TCGv_i32 tdf;
>>> +
>>> +    if (!check_msa_access(ctx)) {
>>> +        return false;
>>> +    }
>>> +
>>> +    if (TARGET_LONG_BITS != 64 && a->df == DF_DOUBLE) {
>>> +        /* Double format valid only for MIPS64 */
>>> +        gen_reserved_instruction(ctx);
>>> +        return true;
>>> +    }
>>
>> I expect this reserved check should be above the MSA is disabled check,
>> within check_msa_access.
>>
>>> +    twd = tcg_const_i32(a->wd);
>>> +    tws = tcg_const_i32(a->ws);
>>
>> tcg_constant_i32.
> 
> Hmm I am confused here, only 'df' is constant, 'ws' is GPR[$rs].
> Since it is limited in [0,32[ and used read-only by the helper,
> we can also pass it as constant?

What?  You're passing the constant ws to the helper, not the contents of the gpr -- that's 
what the helper is expecting.


r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 20/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)
  2021-10-23 21:47 ` [PATCH 20/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Philippe Mathieu-Daudé
@ 2021-10-24 17:37   ` Richard Henderson
  2021-10-24 17:42     ` Richard Henderson
  0 siblings, 1 reply; 78+ messages in thread
From: Richard Henderson @ 2021-10-24 17:37 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> +static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a,
> +                          enum CPUMIPSMSADataFormat df_base,
> +                          void (*gen_msa_3rf)(TCGv_ptr, TCGv_i32, TCGv_i32,
> +                                              TCGv_i32, TCGv_i32))
> +{
> +    TCGv_i32 twd = tcg_const_i32(a->wd);
> +    TCGv_i32 tws = tcg_const_i32(a->ws);
> +    TCGv_i32 twt = tcg_const_i32(a->wt);
> +    /* adjust df value for floating-point instruction */
> +    TCGv_i32 tdf = tcg_constant_i32(a->df + df_base);

I think it would be better to decode df completely in decodetree.
E.g.

%df_hw        21:1 !function=plus_1
@3rf_hw       ...... .... . wt:5 ws:5 wd:5 ......  &msa_r df=%df_hw

%df_wd        21:1 !function=plus_2
@3rf_wd       ...... .... . wt:5 ws:5 wd:5 ......  &msa_r df=%df_wd

Maybe I should get that !expression=(x+1) syntax going soon...

r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 20/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)
  2021-10-24 17:37   ` Richard Henderson
@ 2021-10-24 17:42     ` Richard Henderson
  0 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2021-10-24 17:42 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/24/21 10:37 AM, Richard Henderson wrote:
> On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
>> +static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a,
>> +                          enum CPUMIPSMSADataFormat df_base,
>> +                          void (*gen_msa_3rf)(TCGv_ptr, TCGv_i32, TCGv_i32,
>> +                                              TCGv_i32, TCGv_i32))
>> +{
>> +    TCGv_i32 twd = tcg_const_i32(a->wd);
>> +    TCGv_i32 tws = tcg_const_i32(a->ws);
>> +    TCGv_i32 twt = tcg_const_i32(a->wt);
>> +    /* adjust df value for floating-point instruction */
>> +    TCGv_i32 tdf = tcg_constant_i32(a->df + df_base);
> 
> I think it would be better to decode df completely in decodetree.
> E.g.
> 
> %df_hw        21:1 !function=plus_1
> @3rf_hw       ...... .... . wt:5 ws:5 wd:5 ......  &msa_r df=%df_hw
> 
> %df_wd        21:1 !function=plus_2
> @3rf_wd       ...... .... . wt:5 ws:5 wd:5 ......  &msa_r df=%df_wd

Meant to say, with that changed,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 21/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)
  2021-10-23 21:47 ` [PATCH 21/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) Philippe Mathieu-Daudé
@ 2021-10-24 17:42   ` Richard Henderson
  0 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2021-10-24 17:42 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> Convert 3-register floating-point or fixed-point operations
> to decodetree.
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/tcg/msa.decode      |  37 ++++++
>   target/mips/tcg/msa_translate.c | 213 ++++++--------------------------
>   2 files changed, 74 insertions(+), 176 deletions(-)

With the decode fixed as per the previous,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 22/33] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)
  2021-10-23 21:47 ` [PATCH 22/33] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) Philippe Mathieu-Daudé
@ 2021-10-24 17:51   ` Richard Henderson
  2021-10-24 17:52   ` Richard Henderson
  1 sibling, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2021-10-24 17:51 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> +    TCGv_i32 twd = tcg_const_i32(a->wd);
> +    TCGv_i32 tws = tcg_const_i32(a->ws);
> +    TCGv_i32 twt = tcg_const_i32(a->wt);

tcg_constant_i32, otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 22/33] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)
  2021-10-23 21:47 ` [PATCH 22/33] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) Philippe Mathieu-Daudé
  2021-10-24 17:51   ` Richard Henderson
@ 2021-10-24 17:52   ` Richard Henderson
  2021-10-24 18:57     ` Philippe Mathieu-Daudé
  1 sibling, 1 reply; 78+ messages in thread
From: Richard Henderson @ 2021-10-24 17:52 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> +static bool trans_msa_3r_df(DisasContext *ctx, arg_msa_r *a,
> +                            void (*gen_msa_3r_df)(TCGv_ptr, TCGv_i32, TCGv_i32,
> +                                                  TCGv_i32, TCGv_i32))
> +{
> +    TCGv_i32 tdf = tcg_constant_i32(a->df);
> +    TCGv_i32 twd = tcg_const_i32(a->wd);
> +    TCGv_i32 tws = tcg_const_i32(a->ws);
> +    TCGv_i32 twt = tcg_const_i32(a->wt);
> +
> +    gen_msa_3r_df(cpu_env, tdf, twd, tws, twt);

Missing check_msa_access.

r~



^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 23/33] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)
  2021-10-23 21:47 ` [PATCH 23/33] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Philippe Mathieu-Daudé
@ 2021-10-24 17:55   ` Richard Henderson
  0 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2021-10-24 17:55 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> +static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a,
> +                         void (*gen_msa_3r_b)(TCGv_ptr, TCGv_i32,
> +                                              TCGv_i32, TCGv_i32),
> +                         void (*gen_msa_3r_h)(TCGv_ptr, TCGv_i32,
> +                                              TCGv_i32, TCGv_i32),
> +                         void (*gen_msa_3r_w)(TCGv_ptr, TCGv_i32,
> +                                              TCGv_i32, TCGv_i32),
> +                         void (*gen_msa_3r_d)(TCGv_ptr, TCGv_i32,
> +                                              TCGv_i32, TCGv_i32))

Use a table, like before.

> +{
> +    TCGv_i32 twd = tcg_const_i32(a->wd);
> +    TCGv_i32 tws = tcg_const_i32(a->ws);
> +    TCGv_i32 twt = tcg_const_i32(a->wt);

tcg_constant_i32.

Check for NULL and return false, then do check_msa_access.

r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 24/33] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)
  2021-10-23 21:47 ` [PATCH 24/33] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) Philippe Mathieu-Daudé
@ 2021-10-24 18:09   ` Richard Henderson
  0 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2021-10-24 18:09 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> Convert BINSL (Vector Bit Insert Left) and BINSR (Vector Bit
> Insert Right) opcodes to decodetree.
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/tcg/msa.decode      |  3 +++
>   target/mips/tcg/msa_translate.c | 37 +++------------------------------
>   2 files changed, 6 insertions(+), 34 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 25/33] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4)
  2021-10-23 21:47 ` [PATCH 25/33] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) Philippe Mathieu-Daudé
@ 2021-10-24 18:12   ` Richard Henderson
  0 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2021-10-24 18:12 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> Convert 3-register operations to decodetree.
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/tcg/msa.decode      |  53 ++
>   target/mips/tcg/msa_translate.c | 916 ++------------------------------
>   2 files changed, 106 insertions(+), 863 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree
  2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
                   ` (32 preceding siblings ...)
  2021-10-23 21:48 ` [PATCH 33/33] target/mips: Adjust style in msa_translate_init() Philippe Mathieu-Daudé
@ 2021-10-24 18:26 ` Jiaxun Yang
  2021-10-24 19:01   ` Philippe Mathieu-Daudé
  33 siblings, 1 reply; 78+ messages in thread
From: Jiaxun Yang @ 2021-10-24 18:26 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel
  Cc: Aleksandar Rikalo, Richard Henderson, Luis Pires


在 2021/10/23 22:47, Philippe Mathieu-Daudé 写道:
> Hi,
>
>
>
> This series converts 2000+ lines of switch() code to decodetree
>
> description, so this hard-to-review/modify switch is auto generated
>
> by the decodetree script. This is a big win for maintenance (and
>
> indeed the convertion revealed 2 bugs).
>
>
>
> Massive convertions are - beside being often boring - bug-prone.
>
> In this series we re-start running the MSA tests (the tests are
>
> run automagically in the 'build-user-static' job on gitlab CI).
>
>
>
> Although boring, the conversion is very clean, so I hope it will
>
> be easy enough to review. The TRANS*() macros are heavily used.
>
>
>
> When possible, constant fields are hold with tcg_constant().
>
>
>
> Note, various opcodes can be optimized using TCG host vectors.
>
> We won't address that in this series, as it makes the resulting
>
> review harder. We will post that in a following series. Here we
>
> simply dummy-convert.
>
>
>
> The resulting msa.decode file is quite pleasant to look at, and
>
> the diff-stat is encouraging: number of LoC halved.
>
>
>
> Regards,

Thanks that's really helpful!

For the whole series:

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

Double checked decode tree opcode with manual.

Thanks.

- Jiaxun

>
>
>
> Phil.
>
>
>
> git: https://gitlab.com/philmd/qemu.git tree/mips-msa-decodetree
>
> Based-on: <20211023164329.328137-1-f4bug@amsat.org>
>
>
>
> Philippe Mathieu-Daudé (33):
>
>    tests/tcg: Fix some targets default cross compiler path
>
>    target/mips: Fix MSA MADDV.B opcode
>
>    target/mips: Fix MSA MSUBV.B opcode
>
>    tests/tcg/mips: Run MSA opcodes tests on user-mode emulation
>
>    target/mips: Have check_msa_access() return a boolean
>
>    target/mips: Use enum definitions from CPUMIPSMSADataFormat enum
>
>    target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v
>
>    target/mips: Convert MSA LDI opcode to decodetree
>
>    target/mips: Introduce generic TRANS_CHECK() for decodetree helpers
>
>    target/mips: Extract df_extract() helper
>
>    target/mips: Convert MSA I5 instruction format to decodetree
>
>    target/mips: Convert MSA BIT instruction format to decodetree
>
>    target/mips: Convert MSA SHF opcode to decodetree
>
>    target/mips: Convert MSA I8 instruction format to decodetree
>
>    target/mips: Convert MSA load/store instruction format to decodetree
>
>    target/mips: Convert MSA 2RF instruction format to decodetree
>
>    target/mips: Convert MSA FILL opcode to decodetree
>
>    target/mips: Convert MSA 2R instruction format to decodetree
>
>    target/mips: Convert MSA VEC instruction format to decodetree
>
>    target/mips: Convert MSA 3RF instruction format to decodetree
>
>      (DF_HALF)
>
>    target/mips: Convert MSA 3RF instruction format to decodetree
>
>      (DF_WORD)
>
>    target/mips: Convert MSA 3R instruction format to decodetree (part
>
>      1/4)
>
>    target/mips: Convert MSA 3R instruction format to decodetree (part
>
>      2/4)
>
>    target/mips: Convert MSA 3R instruction format to decodetree (part
>
>      3/4)
>
>    target/mips: Convert MSA 3R instruction format to decodetree (part
>
>      4/4)
>
>    target/mips: Convert MSA ELM instruction format to decodetree
>
>    target/mips: Convert MSA COPY_U opcode to decodetree
>
>    target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree
>
>    target/mips: Convert MSA MOVE.V opcode to decodetree
>
>    target/mips: Convert CFCMSA and CTCMSA opcodes to decodetree
>
>    target/mips: Remove generic MSA opcode
>
>    target/mips: Remove one MSA unnecessary decodetree overlap group
>
>    target/mips: Adjust style in msa_translate_init()
>
>
>
>   tests/tcg/mips/ase-msa.mak         |   30 +
>
>   target/mips/tcg/translate.h        |    9 +
>
>   target/mips/tcg/msa.decode         |  231 ++-
>
>   target/mips/tcg/msa_helper.c       |   64 +-
>
>   target/mips/tcg/msa_translate.c    | 2781 +++++++---------------------
>
>   MAINTAINERS                        |    1 +
>
>   tests/tcg/configure.sh             |   14 +-
>
>   tests/tcg/mips/Makefile.target     |    5 +
>
>   tests/tcg/mips64/Makefile.target   |    9 +
>
>   tests/tcg/mips64el/Makefile.target |   12 +
>
>   tests/tcg/mipsel/Makefile.target   |    9 +
>
>   11 files changed, 1052 insertions(+), 2113 deletions(-)
>
>   create mode 100644 tests/tcg/mips/ase-msa.mak
>
>   create mode 100644 tests/tcg/mips64/Makefile.target
>
>   create mode 100644 tests/tcg/mips64el/Makefile.target
>
>   create mode 100644 tests/tcg/mipsel/Makefile.target
>
>
>


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 22/33] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)
  2021-10-24 17:52   ` Richard Henderson
@ 2021-10-24 18:57     ` Philippe Mathieu-Daudé
  2021-10-24 20:27       ` Richard Henderson
  0 siblings, 1 reply; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-24 18:57 UTC (permalink / raw)
  To: Richard Henderson, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/24/21 19:52, Richard Henderson wrote:
> On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
>> +static bool trans_msa_3r_df(DisasContext *ctx, arg_msa_r *a,
>> +                            void (*gen_msa_3r_df)(TCGv_ptr, TCGv_i32,
>> TCGv_i32,
>> +                                                  TCGv_i32, TCGv_i32))
>> +{
>> +    TCGv_i32 tdf = tcg_constant_i32(a->df);
>> +    TCGv_i32 twd = tcg_const_i32(a->wd);
>> +    TCGv_i32 tws = tcg_const_i32(a->ws);
>> +    TCGv_i32 twt = tcg_const_i32(a->wt);
>> +
>> +    gen_msa_3r_df(cpu_env, tdf, twd, tws, twt);
> 
> Missing check_msa_access.

It is included in TRANS_MSA(). How could I make that clearer?

The style I follow is:
- trans_UPPER() -> direct implementation
- trans_lower() -> called via TRANS_xxx() macro


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree
  2021-10-24 18:26 ` [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Jiaxun Yang
@ 2021-10-24 19:01   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-24 19:01 UTC (permalink / raw)
  To: Jiaxun Yang, qemu-devel; +Cc: Aleksandar Rikalo, Richard Henderson, Luis Pires

On 10/24/21 20:26, Jiaxun Yang wrote:

> Thanks that's really helpful!
> 
> For the whole series:
> 
> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> 
> Double checked decode tree opcode with manual.

Thank you!

I'll respin addressing Richard comments but won't change the
msa.decode file, so I'll include your R-b tag.

Regards,

Phil.


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 22/33] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)
  2021-10-24 18:57     ` Philippe Mathieu-Daudé
@ 2021-10-24 20:27       ` Richard Henderson
  0 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2021-10-24 20:27 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/24/21 11:57 AM, Philippe Mathieu-Daudé wrote:
> On 10/24/21 19:52, Richard Henderson wrote:
>> On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
>>> +static bool trans_msa_3r_df(DisasContext *ctx, arg_msa_r *a,
>>> +                            void (*gen_msa_3r_df)(TCGv_ptr, TCGv_i32,
>>> TCGv_i32,
>>> +                                                  TCGv_i32, TCGv_i32))
>>> +{
>>> +    TCGv_i32 tdf = tcg_constant_i32(a->df);
>>> +    TCGv_i32 twd = tcg_const_i32(a->wd);
>>> +    TCGv_i32 tws = tcg_const_i32(a->ws);
>>> +    TCGv_i32 twt = tcg_const_i32(a->wt);
>>> +
>>> +    gen_msa_3r_df(cpu_env, tdf, twd, tws, twt);
>>
>> Missing check_msa_access.
> 
> It is included in TRANS_MSA(). How could I make that clearer?
> 
> The style I follow is:
> - trans_UPPER() -> direct implementation
> - trans_lower() -> called via TRANS_xxx() macro

Hmm.  I dunno.  Especially since some of the cases require checking for the null function 
pointer *before* the access check.

How many trans helpers do you wind up with in the end?
Perhaps drop TRANS_MSA entirely?


r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 26/33] target/mips: Convert MSA ELM instruction format to decodetree
  2021-10-23 21:47 ` [PATCH 26/33] target/mips: Convert MSA ELM instruction format to decodetree Philippe Mathieu-Daudé
@ 2021-10-24 20:52   ` Richard Henderson
  2021-10-27 17:27     ` Philippe Mathieu-Daudé
  0 siblings, 1 reply; 78+ messages in thread
From: Richard Henderson @ 2021-10-24 20:52 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> +static bool trans_msa_elm_df(DisasContext *ctx, arg_msa_elm *a,
> +                             void (*gen_msa_elm_df)(TCGv_ptr, TCGv_i32,
> +                                                    TCGv_i32, TCGv_i32,
> +                                                    TCGv_i32))
> +{
> +    TCGv_i32 twd;
> +    TCGv_i32 tws;
> +    TCGv_i32 tdf;
> +    TCGv_i32 tn;
> +    uint32_t df, n;
> +
> +    if (!df_extract(df_elm, a->df, &df, &n)) {
> +        gen_reserved_instruction(ctx);
> +        return true;
> +    }

Again, I think this should happen before the access check.

You could even return false from these extractions, because they represent an invalid 
encoding for this instruction.  In a different context, there could be another grouped 
insn that matches.


> +    twd = tcg_const_i32(a->wd);
> +    tws = tcg_const_i32(a->ws);

tcg_constant_i32.

r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 27/33] target/mips: Convert MSA COPY_U opcode to decodetree
  2021-10-23 21:47 ` [PATCH 27/33] target/mips: Convert MSA COPY_U opcode " Philippe Mathieu-Daudé
@ 2021-10-24 21:01   ` Richard Henderson
  2021-10-27 17:40     ` Philippe Mathieu-Daudé
  0 siblings, 1 reply; 78+ messages in thread
From: Richard Henderson @ 2021-10-24 21:01 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> +#define TRANS_DF_W64(NAME, trans_func, gen_func) \
> +        TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
> +                    DF_HALF, DF_WORD, \
> +                    gen_func##_b, gen_func##_h, gen_func##_w, NULL)

Again with the table.

> +static bool trans_msa_elm_d64(DisasContext *ctx, arg_msa_elm *a,
> +                              enum CPUMIPSMSADataFormat df_max32,
> +                              enum CPUMIPSMSADataFormat df_max64,

I think you should just arrange for the entries in the table to be null when the element 
variant is not defined.

> +    twd = tcg_const_i32(a->wd);
> +    tws = tcg_const_i32(a->ws);

tcg_constant_i32.


r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 28/33] target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree
  2021-10-23 21:47 ` [PATCH 28/33] target/mips: Convert MSA COPY_S and INSERT opcodes " Philippe Mathieu-Daudé
@ 2021-10-24 21:02   ` Richard Henderson
  0 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2021-10-24 21:02 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> Convert the COPY_S (Element Copy to GPR Signed) opcode
> and INSERT (GPR Insert Element) opcode to decodetree.
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/tcg/msa.decode      |  2 +
>   target/mips/tcg/msa_translate.c | 92 ++++-----------------------------
>   2 files changed, 12 insertions(+), 82 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 29/33] target/mips: Convert MSA MOVE.V opcode to decodetree
  2021-10-23 21:47 ` [PATCH 29/33] target/mips: Convert MSA MOVE.V opcode " Philippe Mathieu-Daudé
@ 2021-10-24 21:09   ` Richard Henderson
  0 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2021-10-24 21:09 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> +    tsr = tcg_const_i32(a->ws);
> +    tdt = tcg_const_i32(a->wd);

tcg_constant_i32.  Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 30/33] target/mips: Convert CFCMSA and CTCMSA opcodes to decodetree
  2021-10-23 21:48 ` [PATCH 30/33] target/mips: Convert CFCMSA and CTCMSA opcodes " Philippe Mathieu-Daudé
@ 2021-10-24 21:15   ` Richard Henderson
  0 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2021-10-24 21:15 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:48 PM, Philippe Mathieu-Daudé wrote:
> Convert the CFCMSA (Copy From Control MSA register) and
> CTCMSA (Copy To Control MSA register) opcodes to decodetree.
> 
> Since they respectively overlap with the SLDI and SPLATI
> opcodes, use decodetree overlap groups.
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/tcg/msa.decode      | 10 +++-
>   target/mips/tcg/msa_translate.c | 95 ++++++++++++---------------------
>   2 files changed, 42 insertions(+), 63 deletions(-)

There are a couple of tcg_const_i32 that should be tcg_constant_i32, but otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~



^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 31/33] target/mips: Remove generic MSA opcode
  2021-10-23 21:48 ` [PATCH 31/33] target/mips: Remove generic MSA opcode Philippe Mathieu-Daudé
@ 2021-10-24 21:16   ` Richard Henderson
  0 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2021-10-24 21:16 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:48 PM, Philippe Mathieu-Daudé wrote:
> All opcodes have been converted to decodetree. The generic
> MSA handler is now pointless, remove it.
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/tcg/msa.decode      | 2 --
>   target/mips/tcg/msa_translate.c | 7 -------
>   2 files changed, 9 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 32/33] target/mips: Remove one MSA unnecessary decodetree overlap group
  2021-10-23 21:48 ` [PATCH 32/33] target/mips: Remove one MSA unnecessary decodetree overlap group Philippe Mathieu-Daudé
@ 2021-10-24 21:17   ` Richard Henderson
  0 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2021-10-24 21:17 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:48 PM, Philippe Mathieu-Daudé wrote:
> Only the MSA generic opcode was overlapping with the other
> instructions. Since the previous commit removed it, we can
> now remove the overlap group. The decodetree script forces
> us to re-indent the opcodes.
> 
> Diff trivial to review using `git-diff --ignore-all-space`.
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/tcg/msa.decode | 398 ++++++++++++++++++-------------------
>   1 file changed, 198 insertions(+), 200 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 33/33] target/mips: Adjust style in msa_translate_init()
  2021-10-23 21:48 ` [PATCH 33/33] target/mips: Adjust style in msa_translate_init() Philippe Mathieu-Daudé
@ 2021-10-24 21:18   ` Richard Henderson
  0 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2021-10-24 21:18 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/23/21 2:48 PM, Philippe Mathieu-Daudé wrote:
> While the first 'off' variable assignment is unused, it helps
> to better understand the code logic. Move the assignation where
> it would have been used so it is easier to compare the MSA
> registers based on FPU ones versus the MSA specific registers.
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/tcg/msa_translate.c | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 17/33] target/mips: Convert MSA FILL opcode to decodetree
  2021-10-24 17:26       ` Richard Henderson
@ 2021-10-25 16:43         ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-25 16:43 UTC (permalink / raw)
  To: Richard Henderson, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/24/21 19:26, Richard Henderson wrote:
> On 10/24/21 9:44 AM, Philippe Mathieu-Daudé wrote:
>> On 10/24/21 07:04, Richard Henderson wrote:
>>> On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
>>>> Convert the FILL opcode (Vector Fill from GPR) to decodetree.
>>>>
>>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>>> ---
>>>>    target/mips/tcg/msa.decode      |  2 ++
>>>>    target/mips/tcg/msa_translate.c | 40
>>>> +++++++++++++++++++++++----------
>>>>    2 files changed, 30 insertions(+), 12 deletions(-)
>>
>>>>    +static bool trans_FILL(DisasContext *ctx, arg_msa_r *a)
>>>> +{
>>>> +    TCGv_i32 twd;
>>>> +    TCGv_i32 tws;
>>>> +    TCGv_i32 tdf;
>>>> +
>>>> +    if (!check_msa_access(ctx)) {
>>>> +        return false;
>>>> +    }
>>>> +
>>>> +    if (TARGET_LONG_BITS != 64 && a->df == DF_DOUBLE) {
>>>> +        /* Double format valid only for MIPS64 */
>>>> +        gen_reserved_instruction(ctx);
>>>> +        return true;
>>>> +    }
>>>
>>> I expect this reserved check should be above the MSA is disabled check,
>>> within check_msa_access.
>>>
>>>> +    twd = tcg_const_i32(a->wd);
>>>> +    tws = tcg_const_i32(a->ws);
>>>
>>> tcg_constant_i32.
>>
>> Hmm I am confused here, only 'df' is constant, 'ws' is GPR[$rs].
>> Since it is limited in [0,32[ and used read-only by the helper,
>> we can also pass it as constant?
> 
> What?  You're passing the constant ws to the helper, not the contents of
> the gpr -- that's what the helper is expecting.

OK got it now, thanks :)


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 04/33] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation
  2021-10-23 21:47 ` [PATCH 04/33] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation Philippe Mathieu-Daudé
@ 2021-10-27 10:38   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 10:38 UTC (permalink / raw)
  To: qemu-devel
  Cc: Alex Bennée, Aleksandar Rikalo, Richard Henderson, Luis Pires

On 10/23/21 23:47, Philippe Mathieu-Daudé wrote:
> The following commits added various user-mode tests
> for various MSA instructions:
> 
>  - 0fdd986a6c8 ("Add tests for MSA integer add instructions")
>  - 1be82d89011 ("Add tests for MSA integer average instructions")
>  - 1d336c87a3c ("Add tests for MSA bit set instructions")
>  - 1e6bea794c8 ("Add tests for MSA integer max/min instructions")
>  - 2a367db039f ("Add tests for MSA pack instructions")
>  - 3d9569b8550 ("Add tests for MSA move instructions")
>  - 4b302ce90db ("Add tests for MSA integer multiply instructions")
>  - 520e210c0aa ("Add tests for MSA integer compare instructions")
>  - 53e116fed6d ("Add tests for MSA integer subtract instructions")
>  - 666952ea7c1 ("Add tests for MSA bit move instructions")
>  - 72f463bc080 ("Add tests for MSA integer divide instructions")
>  - 8598f5fac1c ("Add tests for MSA FP max/min instructions")
>  - 99d423e576a ("Add tests for MSA shift instructions")
>  - a8f91dd9fd0 ("Add tests for MSA integer dot product instructions")
>  - b62592ab655 ("Add tests for MSA bit counting instructions")
>  - ba632924450 ("Add tests for MSA logic instructions")
>  - fc76f486677 ("Add tests for MSA interleave instructions")
> 
> Cover them in the buildsys machinery so they are run automatically
> when calling 'make check-tcg'.
> 
> Start running them on the mips64el target.
> 
> Cc: Alex Bennée <alex.bennee@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  tests/tcg/mips/ase-msa.mak         | 30 ++++++++++++++++++++++++++++++
>  MAINTAINERS                        |  1 +
>  tests/tcg/mips/Makefile.target     |  5 +++++
>  tests/tcg/mips64/Makefile.target   |  9 +++++++++
>  tests/tcg/mips64el/Makefile.target | 12 ++++++++++++
>  tests/tcg/mipsel/Makefile.target   |  9 +++++++++
>  6 files changed, 66 insertions(+)
>  create mode 100644 tests/tcg/mips/ase-msa.mak
>  create mode 100644 tests/tcg/mips64/Makefile.target
>  create mode 100644 tests/tcg/mips64el/Makefile.target
>  create mode 100644 tests/tcg/mipsel/Makefile.target
> 
> diff --git a/tests/tcg/mips/ase-msa.mak b/tests/tcg/mips/ase-msa.mak
> new file mode 100644
> index 00000000000..be1ba967a5b
> --- /dev/null
> +++ b/tests/tcg/mips/ase-msa.mak
> @@ -0,0 +1,30 @@
> +# -*- Mode: makefile -*-
> +#
> +# MIPS MSA specific TCG tests
> +#
> +# Copyright (c) 2021 Philippe Mathieu-Daudé <f4bug@amsat.org>
> +#
> +# SPDX-License-Identifier: GPL-2.0-or-later
> +
> +MSA_DIR = $(SRC_PATH)/tests/tcg/mips/user/ase/msa
> +
> +MSA_TEST_CLASS = bit-count bit-move bit-set fixed-multiply \
> +				float-max-min int-add int-average int-compare int-divide \
> +				int-dot-product interleave int-max-min int-modulo \
> +				int-multiply int-subtract logic move pack shift
> +
> +MSA_TEST_SRCS = $(foreach class,$(MSA_TEST_CLASS),$(wildcard $(MSA_DIR)/$(class)/*.c))
> +
> +MSA_TESTS = $(patsubst %.c,%,$(notdir $(MSA_TEST_SRCS)))
> +
> +$(MSA_TESTS): CFLAGS+=-mmsa $(MSA_CFLAGS)
> +$(MSA_TESTS): %: $(foreach CLASS,$(MSA_TEST_CLASS),$(wildcard $(MSA_DIR)/$(CLASS)/%.c))
> +	$(CC) -static $(CFLAGS) -o $@ \
> +		$(foreach CLASS,$(MSA_TEST_CLASS),$(wildcard $(MSA_DIR)/$(CLASS)/$@.c))

FYI I am using $wilcard because because the test files are in multiple
directories ($MSA_TEST_CLASS).

> +
> +$(foreach test,$(MSA_TESTS),run-$(test)): QEMU_OPTS += -cpu $(MSA_CPU)
> +
> +# FIXME: These tests fail when using plugins
> +ifneq ($(CONFIG_PLUGIN),y)
> +TESTS += $(MSA_TESTS)
> +endif
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 4e77d03651b..53c6c549b80 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -3111,6 +3111,7 @@ R: Jiaxun Yang <jiaxun.yang@flygoat.com>
>  R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
>  S: Odd Fixes
>  F: tcg/mips/
> +F: tests/tcg/mips*
>  
>  PPC TCG target
>  M: Richard Henderson <richard.henderson@linaro.org>
> diff --git a/tests/tcg/mips/Makefile.target b/tests/tcg/mips/Makefile.target
> index 1a994d5525e..191fe179119 100644
> --- a/tests/tcg/mips/Makefile.target
> +++ b/tests/tcg/mips/Makefile.target
> @@ -17,3 +17,8 @@ TESTS += $(MIPS_TESTS)
>  hello-mips: CFLAGS+=-mno-abicalls -fno-PIC -mabi=32
>  hello-mips: LDFLAGS+=-nostdlib
>  endif
> +
> +# FIXME enable MSA tests

This is commented because the Debian toolchain produces:

/usr/mips-linux-gnu/include/gnu/stubs.h:17:11: fatal error:
gnu/stubs-o32_hard_2008.h: No such file or directory
 # include <gnu/stubs-o32_hard_2008.h>
           ^~~~~~~~~~~~~~~~~~~~~~~~~~~

> +#MSA_CFLAGS=-march=mips64r5 -mnan=2008

Here I meant:

   MSA_CFLAGS=-march=mips32r5 -mnan=2008

Anyhow, similar error using -march=mips32r6.

> +#MSA_CPU=P5600
> +#include $(SRC_PATH)/tests/tcg/mips/ase-msa.mak
> diff --git a/tests/tcg/mips64/Makefile.target b/tests/tcg/mips64/Makefile.target
> new file mode 100644
> index 00000000000..d876b92f219
> --- /dev/null
> +++ b/tests/tcg/mips64/Makefile.target
> @@ -0,0 +1,9 @@
> +# -*- Mode: makefile -*-
> +#
> +# mips64el specific TCG tests
> +#
> +# Copyright (c) 2021 Philippe Mathieu-Daudé <f4bug@amsat.org>
> +#
> +# SPDX-License-Identifier: GPL-2.0-or-later
> +
> +# 64-bit MSA is tested on little-endian target
> diff --git a/tests/tcg/mips64el/Makefile.target b/tests/tcg/mips64el/Makefile.target
> new file mode 100644
> index 00000000000..87c0d6dce18
> --- /dev/null
> +++ b/tests/tcg/mips64el/Makefile.target
> @@ -0,0 +1,12 @@
> +# -*- Mode: makefile -*-
> +#
> +# mips64el specific TCG tests
> +#
> +# Copyright (c) 2021 Philippe Mathieu-Daudé <f4bug@amsat.org>
> +#
> +# SPDX-License-Identifier: GPL-2.0-or-later
> +
> +# MSA
> +MSA_CFLAGS=-march=mips64r5 -mnan=legacy
> +MSA_CPU=Loongson-3A4000
> +include $(SRC_PATH)/tests/tcg/mips/ase-msa.mak
> diff --git a/tests/tcg/mipsel/Makefile.target b/tests/tcg/mipsel/Makefile.target
> new file mode 100644
> index 00000000000..c8acacb4497
> --- /dev/null
> +++ b/tests/tcg/mipsel/Makefile.target
> @@ -0,0 +1,9 @@
> +# -*- Mode: makefile -*-
> +#
> +# mipsel specific TCG tests
> +#
> +# Copyright (c) 2021 Philippe Mathieu-Daudé <f4bug@amsat.org>
> +#
> +# SPDX-License-Identifier: GPL-2.0-or-later
> +
> +# 32-bit MSA is tested on big-endian target
> 


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 26/33] target/mips: Convert MSA ELM instruction format to decodetree
  2021-10-24 20:52   ` Richard Henderson
@ 2021-10-27 17:27     ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 17:27 UTC (permalink / raw)
  To: Richard Henderson, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/24/21 22:52, Richard Henderson wrote:
> On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
>> +static bool trans_msa_elm_df(DisasContext *ctx, arg_msa_elm *a,
>> +                             void (*gen_msa_elm_df)(TCGv_ptr, TCGv_i32,
>> +                                                    TCGv_i32, TCGv_i32,
>> +                                                    TCGv_i32))
>> +{
>> +    TCGv_i32 twd;
>> +    TCGv_i32 tws;
>> +    TCGv_i32 tdf;
>> +    TCGv_i32 tn;
>> +    uint32_t df, n;
>> +
>> +    if (!df_extract(df_elm, a->df, &df, &n)) {
>> +        gen_reserved_instruction(ctx);
>> +        return true;
>> +    }
> 
> Again, I think this should happen before the access check.
> 
> You could even return false from these extractions, because they
> represent an invalid encoding for this instruction.  In a different
> context, there could be another grouped insn that matches.

Yes, you are correct.


^ permalink raw reply	[flat|nested] 78+ messages in thread

* Re: [PATCH 27/33] target/mips: Convert MSA COPY_U opcode to decodetree
  2021-10-24 21:01   ` Richard Henderson
@ 2021-10-27 17:40     ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 78+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 17:40 UTC (permalink / raw)
  To: Richard Henderson, qemu-devel; +Cc: Aleksandar Rikalo, Luis Pires

On 10/24/21 23:01, Richard Henderson wrote:
> On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
>> +#define TRANS_DF_W64(NAME, trans_func, gen_func) \
>> +        TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
>> +                    DF_HALF, DF_WORD, \
>> +                    gen_func##_b, gen_func##_h, gen_func##_w, NULL)
> 
> Again with the table.
> 
>> +static bool trans_msa_elm_d64(DisasContext *ctx, arg_msa_elm *a,
>> +                              enum CPUMIPSMSADataFormat df_max32,
>> +                              enum CPUMIPSMSADataFormat df_max64,
> 
> I think you should just arrange for the entries in the table to be null
> when the element variant is not defined.

Clever, thank you!


^ permalink raw reply	[flat|nested] 78+ messages in thread

end of thread, other threads:[~2021-10-27 17:49 UTC | newest]

Thread overview: 78+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 01/33] tests/tcg: Fix some targets default cross compiler path Philippe Mathieu-Daudé
2021-10-23 23:24   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 02/33] target/mips: Fix MSA MADDV.B opcode Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 03/33] target/mips: Fix MSA MSUBV.B opcode Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 04/33] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation Philippe Mathieu-Daudé
2021-10-27 10:38   ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 05/33] target/mips: Have check_msa_access() return a boolean Philippe Mathieu-Daudé
2021-10-24  1:02   ` Richard Henderson
2021-10-24 12:48     ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 06/33] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum Philippe Mathieu-Daudé
2021-10-24  1:03   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 07/33] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v Philippe Mathieu-Daudé
2021-10-24  1:05   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 08/33] target/mips: Convert MSA LDI opcode to decodetree Philippe Mathieu-Daudé
2021-10-24  1:53   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 09/33] target/mips: Introduce generic TRANS_CHECK() for decodetree helpers Philippe Mathieu-Daudé
2021-10-24  1:58   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 10/33] target/mips: Extract df_extract() helper Philippe Mathieu-Daudé
2021-10-24  2:26   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 11/33] target/mips: Convert MSA I5 instruction format to decodetree Philippe Mathieu-Daudé
2021-10-24  2:10   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 12/33] target/mips: Convert MSA BIT " Philippe Mathieu-Daudé
2021-10-24  2:45   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 13/33] target/mips: Convert MSA SHF opcode " Philippe Mathieu-Daudé
2021-10-24  3:40   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 14/33] target/mips: Convert MSA I8 instruction format " Philippe Mathieu-Daudé
2021-10-24  3:45   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 15/33] target/mips: Convert MSA load/store " Philippe Mathieu-Daudé
2021-10-24  4:53   ` Richard Henderson
2021-10-24 11:18     ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 16/33] target/mips: Convert MSA 2RF " Philippe Mathieu-Daudé
2021-10-24  5:01   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 17/33] target/mips: Convert MSA FILL opcode " Philippe Mathieu-Daudé
2021-10-24  5:04   ` Richard Henderson
2021-10-24 16:44     ` Philippe Mathieu-Daudé
2021-10-24 17:26       ` Richard Henderson
2021-10-25 16:43         ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 18/33] target/mips: Convert MSA 2R instruction format " Philippe Mathieu-Daudé
2021-10-24  5:14   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 19/33] target/mips: Convert MSA VEC " Philippe Mathieu-Daudé
2021-10-24  5:17   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 20/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Philippe Mathieu-Daudé
2021-10-24 17:37   ` Richard Henderson
2021-10-24 17:42     ` Richard Henderson
2021-10-23 21:47 ` [PATCH 21/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) Philippe Mathieu-Daudé
2021-10-24 17:42   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 22/33] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) Philippe Mathieu-Daudé
2021-10-24 17:51   ` Richard Henderson
2021-10-24 17:52   ` Richard Henderson
2021-10-24 18:57     ` Philippe Mathieu-Daudé
2021-10-24 20:27       ` Richard Henderson
2021-10-23 21:47 ` [PATCH 23/33] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Philippe Mathieu-Daudé
2021-10-24 17:55   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 24/33] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) Philippe Mathieu-Daudé
2021-10-24 18:09   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 25/33] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) Philippe Mathieu-Daudé
2021-10-24 18:12   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 26/33] target/mips: Convert MSA ELM instruction format to decodetree Philippe Mathieu-Daudé
2021-10-24 20:52   ` Richard Henderson
2021-10-27 17:27     ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 27/33] target/mips: Convert MSA COPY_U opcode " Philippe Mathieu-Daudé
2021-10-24 21:01   ` Richard Henderson
2021-10-27 17:40     ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 28/33] target/mips: Convert MSA COPY_S and INSERT opcodes " Philippe Mathieu-Daudé
2021-10-24 21:02   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 29/33] target/mips: Convert MSA MOVE.V opcode " Philippe Mathieu-Daudé
2021-10-24 21:09   ` Richard Henderson
2021-10-23 21:48 ` [PATCH 30/33] target/mips: Convert CFCMSA and CTCMSA opcodes " Philippe Mathieu-Daudé
2021-10-24 21:15   ` Richard Henderson
2021-10-23 21:48 ` [PATCH 31/33] target/mips: Remove generic MSA opcode Philippe Mathieu-Daudé
2021-10-24 21:16   ` Richard Henderson
2021-10-23 21:48 ` [PATCH 32/33] target/mips: Remove one MSA unnecessary decodetree overlap group Philippe Mathieu-Daudé
2021-10-24 21:17   ` Richard Henderson
2021-10-23 21:48 ` [PATCH 33/33] target/mips: Adjust style in msa_translate_init() Philippe Mathieu-Daudé
2021-10-24 21:18   ` Richard Henderson
2021-10-24 18:26 ` [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Jiaxun Yang
2021-10-24 19:01   ` Philippe Mathieu-Daudé

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