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From: Alistair Francis <alistair23@gmail.com>
To: Alexey Baturo <baturo.alexey@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Richard Henderson <richard.henderson@linaro.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	space.monkey.delivers@gmail.com,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Dave Smith <kupokupokupopo@gmail.com>,
	Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v16 5/8] [RISCV_PM] Print new PM CSRs in QEMU logs
Date: Mon, 25 Oct 2021 11:21:50 +1000	[thread overview]
Message-ID: <CAKmqyKOpJABmUueWwH9HkXcnSgTX5RgD2KEBs8JWFFh=VM1Wyg@mail.gmail.com> (raw)
In-Reply-To: <20211022181910.1999197-6-space.monkey.delivers@gmail.com>

On Sat, Oct 23, 2021 at 4:27 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 6b767a4a0b..16fac64806 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -271,6 +271,13 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
>              CSR_MSCRATCH,
>              CSR_SSCRATCH,
>              CSR_SATP,
> +            CSR_MMTE,
> +            CSR_UPMBASE,
> +            CSR_UPMMASK,
> +            CSR_SPMBASE,
> +            CSR_SPMMASK,
> +            CSR_MPMBASE,
> +            CSR_MPMMASK,
>          };
>
>          for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
> --
> 2.30.2
>
>


  reply	other threads:[~2021-10-25  1:23 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-22 18:19 [PATCH v16 0/8] RISC-V Pointer Masking implementation Alexey Baturo
2021-10-22 18:19 ` [PATCH v16 1/8] [RISCV_PM] Add J-extension into RISC-V Alexey Baturo
2021-10-22 18:19 ` [PATCH v16 2/8] [RISCV_PM] Add CSR defines for RISC-V PM extension Alexey Baturo
2021-10-22 18:19 ` [PATCH v16 3/8] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode Alexey Baturo
2021-10-25  5:53   ` Alistair Francis
2021-10-22 18:19 ` [PATCH v16 4/8] [RISCV_PM] Add J extension state description Alexey Baturo
2021-10-22 18:19 ` [PATCH v16 5/8] [RISCV_PM] Print new PM CSRs in QEMU logs Alexey Baturo
2021-10-25  1:21   ` Alistair Francis [this message]
2021-10-22 18:19 ` [PATCH v16 6/8] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions Alexey Baturo
2021-10-22 18:19 ` [PATCH v16 7/8] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension Alexey Baturo
2021-10-22 18:19 ` [PATCH v16 8/8] [RISCV_PM] Allow experimental J-ext to be turned on Alexey Baturo
2021-10-25  4:16 ` [PATCH v16 0/8] RISC-V Pointer Masking implementation Alistair Francis

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