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From: Alistair Francis <alistair23@gmail.com>
To: Alexey Baturo <baturo.alexey@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Richard Henderson <richard.henderson@linaro.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	space.monkey.delivers@gmail.com,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Dave Smith <kupokupokupopo@gmail.com>,
	Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v16 0/8] RISC-V Pointer Masking implementation
Date: Mon, 25 Oct 2021 14:16:25 +1000	[thread overview]
Message-ID: <CAKmqyKO9Ox7_YSiK68xoEQHe+fDHyVR5yga8nu4jHXGhHeCKFQ@mail.gmail.com> (raw)
In-Reply-To: <20211022181910.1999197-1-space.monkey.delivers@gmail.com>

On Sat, Oct 23, 2021 at 4:23 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> v15:
> Renamed pm into pointer_masking in machine state.
>
> v14:
> Addressed Richard's comments from previous series.
>
> v13:
> Rebased QEMU and addressed Richard's comment.
>
> v12:
> Updated function for adjusting address with pointer masking to allocate and use temp register.
>
> v11:
> Addressed a few style issues Alistair mentioned in the previous review.
>
> If this patch series would be accepted, I think my further attention would be to:
> - Support pm for memory operations for RVV
> - Add proper csr and support pm for memory operations for Hypervisor mode
> - Support address wrapping on unaligned accesses as @Richard mentioned previously
>
> Thanks!
>
> Alexey Baturo (7):
>   [RISCV_PM] Add J-extension into RISC-V
>   [RISCV_PM] Add CSR defines for RISC-V PM extension
>   [RISCV_PM] Support CSRs required for RISC-V PM extension except for
>     the h-mode
>   [RISCV_PM] Add J extension state description
>   [RISCV_PM] Print new PM CSRs in QEMU logs
>   [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of
>     instructions
>   [RISCV_PM] Allow experimental J-ext to be turned on
>
> Anatoly Parshintsev (1):
>   [RISCV_PM] Implement address masking functions required for RISC-V
>     Pointer Masking extension

Thanks!

Applied to riscv-to-apply.next

I added a "target/riscv: " prefix to each patch title to indicate that
the patches are for RISC-V.

Alistair

>
>  target/riscv/cpu.c                      |  13 ++
>  target/riscv/cpu.h                      |  15 ++
>  target/riscv/cpu_bits.h                 |  96 ++++++++
>  target/riscv/cpu_helper.c               |  18 ++
>  target/riscv/csr.c                      | 285 ++++++++++++++++++++++++
>  target/riscv/insn_trans/trans_rva.c.inc |   3 +
>  target/riscv/insn_trans/trans_rvd.c.inc |   2 +
>  target/riscv/insn_trans/trans_rvf.c.inc |   2 +
>  target/riscv/insn_trans/trans_rvi.c.inc |   2 +
>  target/riscv/machine.c                  |  27 +++
>  target/riscv/translate.c                |  43 ++++
>  11 files changed, 506 insertions(+)
>
> --
> 2.30.2
>
>


      parent reply	other threads:[~2021-10-25  4:18 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-22 18:19 Alexey Baturo
2021-10-22 18:19 ` [PATCH v16 1/8] [RISCV_PM] Add J-extension into RISC-V Alexey Baturo
2021-10-22 18:19 ` [PATCH v16 2/8] [RISCV_PM] Add CSR defines for RISC-V PM extension Alexey Baturo
2021-10-22 18:19 ` [PATCH v16 3/8] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode Alexey Baturo
2021-10-25  5:53   ` Alistair Francis
2021-10-22 18:19 ` [PATCH v16 4/8] [RISCV_PM] Add J extension state description Alexey Baturo
2021-10-22 18:19 ` [PATCH v16 5/8] [RISCV_PM] Print new PM CSRs in QEMU logs Alexey Baturo
2021-10-25  1:21   ` Alistair Francis
2021-10-22 18:19 ` [PATCH v16 6/8] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions Alexey Baturo
2021-10-22 18:19 ` [PATCH v16 7/8] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension Alexey Baturo
2021-10-22 18:19 ` [PATCH v16 8/8] [RISCV_PM] Allow experimental J-ext to be turned on Alexey Baturo
2021-10-25  4:16 ` Alistair Francis [this message]

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