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[PATCH v16 0/8] RISC-V Pointer Masking implementation
 2021-10-25  5:53 UTC  (6+ messages)
` [PATCH v16 3/8] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
` [PATCH v16 5/8] [RISCV_PM] Print new PM CSRs in QEMU logs

[PATCH 0/9] Configurable policy for handling unstable interfaces
 2021-10-25  5:25 UTC  (10+ messages)
` [PATCH 1/9] qapi: New special feature flag "unstable"
` [PATCH 2/9] qapi: Mark unstable QMP parts with feature 'unstable'
` [PATCH 3/9] qapi: Eliminate QCO_NO_OPTIONS for a slight simplification
` [PATCH 4/9] qapi: Tools for sets of special feature flags in generated code
` [PATCH 5/9] qapi: Generalize struct member policy checking
` [PATCH 6/9] qapi: Generalize command "
` [PATCH 7/9] qapi: Generalize enum member "
` [PATCH 8/9] qapi: Factor out compat_policy_input_ok()
` [PATCH 9/9] qapi: Extend -compat to set policy for unstable interfaces

[PATCH v4 0/5] qapi: Add feature flags to enum members
 2021-10-25  4:34 UTC  (7+ messages)
` [PATCH v4 1/5] qapi: Enable enum member introspection to show more than name
` [PATCH v4 2/5] qapi: Add feature flags to enum members
` [PATCH v4 3/5] qapi: Move compat policy from QObject to generic visitor
` [PATCH v4 4/5] qapi: Implement deprecated-input={reject, crash} for enum values
` [PATCH v4 5/5] block: Deprecate transaction type drive-backup

[PATCH v3 0/5] qapi: Add feature flags to enum members
 2021-10-25  4:31 UTC  (3+ messages)
` [PATCH v3 1/5] qapi: Enable enum member introspection to show more than name

[Bug 1761798] Re: live migration intermittently fails in CI with "VQ 0 size 0x80 Guest index 0x12c inconsistent with Host index 0x134: delta 0xfff8"
 2021-10-25  4:17 UTC  (2+ messages)

[PATCH] hw/riscv: opentitan: Fixup the PLIC context addresses
 2021-10-25  4:16 UTC  (2+ messages)

gitlab/cirrus auth token failure
 2021-10-25  1:15 UTC  (3+ messages)

[PATCH 0/4] target/alpha,arm,ppc: More uses of tcg_constant()
 2021-10-25  0:21 UTC  (11+ messages)
` [PATCH 1/4] target/alpha: Use tcg_constant_i64() in gen_call_pal()
` [PATCH 2/4] target/arm: Use tcg_constant_i64() in do_sat_addsub_64()
` [PATCH 3/4] target/ppc: Use tcg_constant_tl() in gen_op_cmp()
` [PATCH 4/4] target/ppc: Use tcg_constant_i32() in gen_ld/st()

UASP and Streams
 2021-10-24 22:52 UTC 

[PATCH v3 00/21] Adding partial support for 128-bit riscv target
 2021-10-24 22:49 UTC  (4+ messages)
` [PATCH v3 13/21] target/riscv: support for 128-bit shift instructions

[PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree
 2021-10-24 21:18 UTC  (74+ messages)
` [PATCH 01/33] tests/tcg: Fix some targets default cross compiler path
` [PATCH 02/33] target/mips: Fix MSA MADDV.B opcode
` [PATCH 03/33] target/mips: Fix MSA MSUBV.B opcode
` [PATCH 04/33] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation
` [PATCH 05/33] target/mips: Have check_msa_access() return a boolean
` [PATCH 06/33] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum
` [PATCH 07/33] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v
` [PATCH 08/33] target/mips: Convert MSA LDI opcode to decodetree
` [PATCH 09/33] target/mips: Introduce generic TRANS_CHECK() for decodetree helpers
` [PATCH 10/33] target/mips: Extract df_extract() helper
` [PATCH 11/33] target/mips: Convert MSA I5 instruction format to decodetree
` [PATCH 12/33] target/mips: Convert MSA BIT "
` [PATCH 13/33] target/mips: Convert MSA SHF opcode "
` [PATCH 14/33] target/mips: Convert MSA I8 instruction format "
` [PATCH 15/33] target/mips: Convert MSA load/store "
` [PATCH 16/33] target/mips: Convert MSA 2RF "
` [PATCH 17/33] target/mips: Convert MSA FILL opcode "
` [PATCH 18/33] target/mips: Convert MSA 2R instruction format "
` [PATCH 19/33] target/mips: Convert MSA VEC "
` [PATCH 20/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)
` [PATCH 21/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)
` [PATCH 22/33] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)
` [PATCH 23/33] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)
` [PATCH 24/33] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)
` [PATCH 25/33] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4)
` [PATCH 26/33] target/mips: Convert MSA ELM instruction format to decodetree
` [PATCH 27/33] target/mips: Convert MSA COPY_U opcode "
` [PATCH 28/33] target/mips: Convert MSA COPY_S and INSERT opcodes "
` [PATCH 29/33] target/mips: Convert MSA MOVE.V opcode "
` [PATCH 30/33] target/mips: Convert CFCMSA and CTCMSA opcodes "
` [PATCH 31/33] target/mips: Remove generic MSA opcode
` [PATCH 32/33] target/mips: Remove one MSA unnecessary decodetree overlap group
` [PATCH 33/33] target/mips: Adjust style in msa_translate_init()

[PATCH] ui/gtk: Update the refresh rate for gl-area too
 2021-10-24 14:31 UTC 

[PATCH 0/5] hw/sh4: Codeing style fixes
 2021-10-24 14:09 UTC  (7+ messages)
` [PATCH 2/5] hw/sh4: Coding style: Fix multi-line comments
` [PATCH 5/5] hw/sh4: Coding style: Remove unnecessary casts
` [PATCH 4/5] hw/sh4: Coding style: Add missing braces
` [PATCH 1/5] hw/sh4: Coding style: Remove tabs
` [PATCH 3/5] hw/sh4: Coding style: White space fixes

[Bug 1921664] Re: Coroutines are racy for risc64 emu on arm64 - crash on Assertion
 2021-10-24  4:17 UTC  (2+ messages)

[PATCH v2 0/2] vfio: Some fixes about vfio-pci MMIO RAM mapping
 2021-10-24  2:09 UTC  (6+ messages)
` [PATCH v2 1/2] vfio/pci: Fix vfio-pci sub-page MMIO BAR mmaping in live migration

[PATCH v8 00/10] acpi: Error Record Serialization Table, ERST, support for QEMU
 2021-10-24  1:13 UTC  (7+ messages)
` [PATCH v8 07/10] ACPI ERST: create ACPI ERST table for pc/x86 machines

[PULL 00/11] Trivial branch for 6.2 patches
 2021-10-23 23:22 UTC  (13+ messages)
` [PULL 01/11] po: update turkish translation
` [PULL 02/11] disas/nios2: Fix style in print_insn_nios2()
` [PULL 03/11] disas/nios2: Simplify endianess conversion
` [PULL 04/11] MAINTAINERS: Add myself as reviewer of 'Machine core' API
` [PULL 05/11] softmmu/physmem.c: Fix typo in comment
` [PULL 06/11] hw/nvram: Fix Memory Leak in Xilinx eFuse QOM
` [PULL 07/11] hw/nvram: Fix Memory Leak in Xilinx Versal eFuse device
` [PULL 08/11] hw/nvram: Fix Memory Leak in Xilinx ZynqMP "
` [PULL 09/11] README: Fix some documentation URLs
` [PULL 10/11] analyze-migration.py: fix a long standing typo
` [PULL 11/11] analyze-migration.py: fix extract contents ('-x') errors

[PATCH 00/33] PowerISA v3.1 instruction batch
 2021-10-23 21:29 UTC  (39+ messages)
` [PATCH 15/33] target/ppc: Implement Vector Insert from GPR using GPR index insns
` [PATCH 19/33] target/ppc: Implement Vector Extract Double to VSR "
` [PATCH 20/33] target/ppc: Introduce REQUIRE_VSX macro
` [PATCH 21/33] target/ppc: moved stxv and lxv from legacy to decodtree
` [PATCH 22/33] target/ppc: moved stxvx and lxvx "
` [PATCH 23/33] target/ppc: added the instructions LXVP and STXVP
` [PATCH 24/33] target/ppc: added the instructions LXVPX and STXVPX
` [PATCH 25/33] target/ppc: added the instructions PLXV and PSTXV
` [PATCH 26/33] target/ppc: added the instructions PLXVP and PSTXVP
` [PATCH 27/33] target/ppc: moved XXSPLTW to using decodetree
` [PATCH 28/33] target/ppc: moved XXSPLTIB "
` [PATCH 29/33] target/ppc: implemented XXSPLTI32DX
` [PATCH 30/33] target/ppc: Implemented XXSPLTIW using decodetree
` [PATCH 31/33] target/ppc: implemented XXSPLTIDP instruction
` [PATCH 32/33] target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions
` [PATCH 33/33] target/ppc: Implement lxvkq instruction

[RESEND PATCH 0/2] Fix machine parameter default_bus_bypass_iommu
 2021-10-23 20:15 UTC  (5+ messages)
` [RESEND PATCH 2/2] hw/i386: Rename default_bus_bypass_iommu

[PATCH] linux-user/signal: Map exit signals in SIGCHLD siginfo_t
 2021-10-23 19:59 UTC 

[PATCH v3 00/48] tcg: optimize redundant sign extensions
 2021-10-23 18:25 UTC  (4+ messages)
` [PATCH v3 33/48] tcg/optimize: Add type to OptContext

[PATCH] tests/tcg: Fix some targets default cross compiler path
 2021-10-23 18:07 UTC  (3+ messages)

[PATCH 00/24] bsd-user: arm (32-bit) support
 2021-10-23 15:17 UTC  (12+ messages)
` [PATCH 03/24] bsd-user/arm/target_arch_cpu.c: Target specific TLS routines
` [PATCH 04/24] bsd-user/arm/target_arch_cpu.h: CPU Loop definitions
` [PATCH 05/24] bsd-user/arm/target_arch_cpu.h: Implement target_cpu_clone_regs
` [PATCH 06/24] bsd-user/arm/target_arch_cpu.h: Dummy target_cpu_loop implementation
` [PATCH 09/24] bsd-user/arm/target_arch_cpu.h: Implement system call dispatch

Looking for advise on debugging a non-boot kernel on qemu-system-sh4
 2021-10-23 13:22 UTC  (11+ messages)

[PATCH 0/3] target/mips: MSA opcode fixes
 2021-10-23 12:31 UTC  (4+ messages)
` [PATCH 3/3] target/mips: Fix Loongson-3A4000 MSAIR config register

[PATCH v3 00/22] QEMU RISC-V AIA support
 2021-10-23  8:46 UTC  (23+ messages)
` [PATCH v3 01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
` [PATCH v3 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs
` [PATCH v3 03/22] target/riscv: Implement hgeie and hgeip CSRs
` [PATCH v3 04/22] target/riscv: Improve delivery of guest external interrupts
` [PATCH v3 05/22] target/riscv: Allow setting CPU feature from machine/device emulation
` [PATCH v3 06/22] target/riscv: Add AIA cpu feature
` [PATCH v3 07/22] target/riscv: Add defines for AIA CSRs
` [PATCH v3 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback
` [PATCH v3 09/22] target/riscv: Implement AIA local interrupt priorities
` [PATCH v3 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
` [PATCH v3 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs
` [PATCH v3 12/22] target/riscv: Implement AIA interrupt filtering CSRs
` [PATCH v3 13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
` [PATCH v3 14/22] target/riscv: Implement AIA xiselect and xireg CSRs
` [PATCH v3 15/22] target/riscv: Implement AIA IMSIC interface CSRs
` [PATCH v3 16/22] hw/riscv: virt: Use AIA INTC compatible string when available
` [PATCH v3 17/22] target/riscv: Allow users to force enable AIA CSRs in HART
` [PATCH v3 18/22] hw/intc: Add RISC-V AIA APLIC device emulation
` [PATCH v3 19/22] hw/riscv: virt: Add optional AIA APLIC support to virt machine
` [PATCH v3 20/22] hw/intc: Add RISC-V AIA IMSIC device emulation
` [PATCH v3 21/22] hw/riscv: virt: Add optional AIA IMSIC support to virt machine
` [PATCH v3 22/22] docs/system: riscv: Document AIA options for "

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