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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
	"Luis Pires" <luis.pires@eldorado.org.br>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PATCH 32/33] target/mips: Remove one MSA unnecessary decodetree overlap group
Date: Sat, 23 Oct 2021 23:48:02 +0200	[thread overview]
Message-ID: <20211023214803.522078-33-f4bug@amsat.org> (raw)
In-Reply-To: <20211023214803.522078-1-f4bug@amsat.org>

Only the MSA generic opcode was overlapping with the other
instructions. Since the previous commit removed it, we can
now remove the overlap group. The decodetree script forces
us to re-indent the opcodes.

Diff trivial to review using `git-diff --ignore-all-space`.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode | 398 ++++++++++++++++++-------------------
 1 file changed, 198 insertions(+), 200 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 8189eae3499..9af995b71b6 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -44,205 +44,203 @@ BNZ_V               010001 01111  ..... ................    @bz_v
 BZ                  010001 110 .. ..... ................    @bz
 BNZ                 010001 111 .. ..... ................    @bz
 
+ANDI                011110 00 ........ ..... .....  000000  @i8
+ORI                 011110 01 ........ ..... .....  000000  @i8
+NORI                011110 10 ........ ..... .....  000000  @i8
+XORI                011110 11 ........ ..... .....  000000  @i8
+BMNZI               011110 00 ........ ..... .....  000001  @i8
+BMZI                011110 01 ........ ..... .....  000001  @i8
+BSELI               011110 10 ........ ..... .....  000001  @i8
+SHF                 011110 .. ........ ..... .....  000010  @i8_df
+
+ADDVI               011110 000 .. ..... ..... ..... 000110  @u5
+SUBVI               011110 001 .. ..... ..... ..... 000110  @u5
+MAXI_S              011110 010 .. ..... ..... ..... 000110  @s5
+MAXI_U              011110 011 .. ..... ..... ..... 000110  @u5
+MINI_S              011110 100 .. ..... ..... ..... 000110  @s5
+MINI_U              011110 101 .. ..... ..... ..... 000110  @u5
+
+CEQI                011110 000 .. ..... ..... ..... 000111  @s5
+CLTI_S              011110 010 .. ..... ..... ..... 000111  @s5
+CLTI_U              011110 011 .. ..... ..... ..... 000111  @u5
+CLEI_S              011110 100 .. ..... ..... ..... 000111  @s5
+CLEI_U              011110 101 .. ..... ..... ..... 000111  @u5
+
+LDI                 011110 110 .. ..........  ..... 000111  @ldi
+
+SLLI                011110 000 ....... ..... .....  001001  @bit
+SRAI                011110 001 ....... ..... .....  001001  @bit
+SRLI                011110 010 ....... ..... .....  001001  @bit
+BCLRI               011110 011 ....... ..... .....  001001  @bit
+BSETI               011110 100 ....... ..... .....  001001  @bit
+BNEGI               011110 101 ....... ..... .....  001001  @bit
+BINSLI              011110 110 ....... ..... .....  001001  @bit
+BINSRI              011110 111 ....... ..... .....  001001  @bit
+
+SAT_S               011110 000 ....... ..... .....  001010  @bit
+SAT_U               011110 001 ....... ..... .....  001010  @bit
+SRARI               011110 010 ....... ..... .....  001010  @bit
+SRLRI               011110 011 ....... ..... .....  001010  @bit
+
+SLL                 011110 000.. ..... ..... .....  001101  @3r
+SRA                 011110 001.. ..... ..... .....  001101  @3r
+SRL                 011110 010.. ..... ..... .....  001101  @3r
+BCLR                011110 011.. ..... ..... .....  001101  @3r
+BSET                011110 100.. ..... ..... .....  001101  @3r
+BNEG                011110 101.. ..... ..... .....  001101  @3r
+BINSL               011110 110.. ..... ..... .....  001101  @3r
+BINSR               011110 111.. ..... ..... .....  001101  @3r
+
+ADDV                011110 000.. ..... ..... .....  001110  @3r
+SUBV                011110 001.. ..... ..... .....  001110  @3r
+MAX_S               011110 010.. ..... ..... .....  001110  @3r
+MAX_U               011110 011.. ..... ..... .....  001110  @3r
+MIN_S               011110 100.. ..... ..... .....  001110  @3r
+MIN_U               011110 101.. ..... ..... .....  001110  @3r
+MAX_A               011110 110.. ..... ..... .....  001110  @3r
+MIN_A               011110 111.. ..... ..... .....  001110  @3r
+
+CEQ                 011110 000.. ..... ..... .....  001111  @3r
+CLT_S               011110 010.. ..... ..... .....  001111  @3r
+CLT_U               011110 011.. ..... ..... .....  001111  @3r
+CLE_S               011110 100.. ..... ..... .....  001111  @3r
+CLE_U               011110 101.. ..... ..... .....  001111  @3r
+
+ADD_A               011110 000.. ..... ..... .....  010000  @3r
+ADDS_A              011110 001.. ..... ..... .....  010000  @3r
+ADDS_S              011110 010.. ..... ..... .....  010000  @3r
+ADDS_U              011110 011.. ..... ..... .....  010000  @3r
+AVE_S               011110 100.. ..... ..... .....  010000  @3r
+AVE_U               011110 101.. ..... ..... .....  010000  @3r
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+AVER_U              011110 111.. ..... ..... .....  010000  @3r
+
+SUBS_S              011110 000.. ..... ..... .....  010001  @3r
+SUBS_U              011110 001.. ..... ..... .....  010001  @3r
+SUBSUS_U            011110 010.. ..... ..... .....  010001  @3r
+SUBSUU_S            011110 011.. ..... ..... .....  010001  @3r
+ASUB_S              011110 100.. ..... ..... .....  010001  @3r
+ASUB_U              011110 101.. ..... ..... .....  010001  @3r
+
+MULV                011110 000.. ..... ..... .....  010010  @3r
+MADDV               011110 001.. ..... ..... .....  010010  @3r
+MSUBV               011110 010.. ..... ..... .....  010010  @3r
+DIV_S               011110 100.. ..... ..... .....  010010  @3r
+DIV_U               011110 101.. ..... ..... .....  010010  @3r
+MOD_S               011110 110.. ..... ..... .....  010010  @3r
+MOD_U               011110 111.. ..... ..... .....  010010  @3r
+
+DOTP_S              011110 000.. ..... ..... .....  010011  @3r
+DOTP_U              011110 001.. ..... ..... .....  010011  @3r
+DPADD_S             011110 010.. ..... ..... .....  010011  @3r
+DPADD_U             011110 011.. ..... ..... .....  010011  @3r
+DPSUB_S             011110 100.. ..... ..... .....  010011  @3r
+DPSUB_U             011110 101.. ..... ..... .....  010011  @3r
+
+SLD                 011110 000 .. ..... ..... ..... 010100  @3r
+SPLAT               011110 001 .. ..... ..... ..... 010100  @3r
+PCKEV               011110 010 .. ..... ..... ..... 010100  @3r
+PCKOD               011110 011 .. ..... ..... ..... 010100  @3r
+ILVL                011110 100 .. ..... ..... ..... 010100  @3r
+ILVR                011110 101 .. ..... ..... ..... 010100  @3r
+ILVEV               011110 110 .. ..... ..... ..... 010100  @3r
+ILVOD               011110 111 .. ..... ..... ..... 010100  @3r
+
+VSHF                011110 000 .. ..... ..... ..... 010101  @3r
+SRAR                011110 001 .. ..... ..... ..... 010101  @3r
+SRLR                011110 010 .. ..... ..... ..... 010101  @3r
+HADD_S              011110 100.. ..... ..... .....  010101  @3r
+HADD_U              011110 101.. ..... ..... .....  010101  @3r
+HSUB_S              011110 110.. ..... ..... .....  010101  @3r
+HSUB_U              011110 111.. ..... ..... .....  010101  @3r
+
 {
-  ANDI              011110 00 ........ ..... .....  000000  @i8
-  ORI               011110 01 ........ ..... .....  000000  @i8
-  NORI              011110 10 ........ ..... .....  000000  @i8
-  XORI              011110 11 ........ ..... .....  000000  @i8
-  BMNZI             011110 00 ........ ..... .....  000001  @i8
-  BMZI              011110 01 ........ ..... .....  000001  @i8
-  BSELI             011110 10 ........ ..... .....  000001  @i8
-  SHF               011110 .. ........ ..... .....  000010  @i8_df
-
-  ADDVI             011110 000 .. ..... ..... ..... 000110  @u5
-  SUBVI             011110 001 .. ..... ..... ..... 000110  @u5
-  MAXI_S            011110 010 .. ..... ..... ..... 000110  @s5
-  MAXI_U            011110 011 .. ..... ..... ..... 000110  @u5
-  MINI_S            011110 100 .. ..... ..... ..... 000110  @s5
-  MINI_U            011110 101 .. ..... ..... ..... 000110  @u5
-
-  CEQI              011110 000 .. ..... ..... ..... 000111  @s5
-  CLTI_S            011110 010 .. ..... ..... ..... 000111  @s5
-  CLTI_U            011110 011 .. ..... ..... ..... 000111  @u5
-  CLEI_S            011110 100 .. ..... ..... ..... 000111  @s5
-  CLEI_U            011110 101 .. ..... ..... ..... 000111  @u5
-
-  LDI               011110 110 .. ..........  ..... 000111  @ldi
-
-  SLLI              011110 000 ....... ..... .....  001001  @bit
-  SRAI              011110 001 ....... ..... .....  001001  @bit
-  SRLI              011110 010 ....... ..... .....  001001  @bit
-  BCLRI             011110 011 ....... ..... .....  001001  @bit
-  BSETI             011110 100 ....... ..... .....  001001  @bit
-  BNEGI             011110 101 ....... ..... .....  001001  @bit
-  BINSLI            011110 110 ....... ..... .....  001001  @bit
-  BINSRI            011110 111 ....... ..... .....  001001  @bit
-
-  SAT_S             011110 000 ....... ..... .....  001010  @bit
-  SAT_U             011110 001 ....... ..... .....  001010  @bit
-  SRARI             011110 010 ....... ..... .....  001010  @bit
-  SRLRI             011110 011 ....... ..... .....  001010  @bit
-
-  SLL               011110 000.. ..... ..... .....  001101  @3r
-  SRA               011110 001.. ..... ..... .....  001101  @3r
-  SRL               011110 010.. ..... ..... .....  001101  @3r
-  BCLR              011110 011.. ..... ..... .....  001101  @3r
-  BSET              011110 100.. ..... ..... .....  001101  @3r
-  BNEG              011110 101.. ..... ..... .....  001101  @3r
-  BINSL             011110 110.. ..... ..... .....  001101  @3r
-  BINSR             011110 111.. ..... ..... .....  001101  @3r
-
-  ADDV              011110 000.. ..... ..... .....  001110  @3r
-  SUBV              011110 001.. ..... ..... .....  001110  @3r
-  MAX_S             011110 010.. ..... ..... .....  001110  @3r
-  MAX_U             011110 011.. ..... ..... .....  001110  @3r
-  MIN_S             011110 100.. ..... ..... .....  001110  @3r
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-  MAX_A             011110 110.. ..... ..... .....  001110  @3r
-  MIN_A             011110 111.. ..... ..... .....  001110  @3r
-
-  CEQ               011110 000.. ..... ..... .....  001111  @3r
-  CLT_S             011110 010.. ..... ..... .....  001111  @3r
-  CLT_U             011110 011.. ..... ..... .....  001111  @3r
-  CLE_S             011110 100.. ..... ..... .....  001111  @3r
-  CLE_U             011110 101.. ..... ..... .....  001111  @3r
-
-  ADD_A             011110 000.. ..... ..... .....  010000  @3r
-  ADDS_A            011110 001.. ..... ..... .....  010000  @3r
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-  ADDS_U            011110 011.. ..... ..... .....  010000  @3r
-  AVE_S             011110 100.. ..... ..... .....  010000  @3r
-  AVE_U             011110 101.. ..... ..... .....  010000  @3r
-  AVER_S            011110 110.. ..... ..... .....  010000  @3r
-  AVER_U            011110 111.. ..... ..... .....  010000  @3r
-
-  SUBS_S            011110 000.. ..... ..... .....  010001  @3r
-  SUBS_U            011110 001.. ..... ..... .....  010001  @3r
-  SUBSUS_U          011110 010.. ..... ..... .....  010001  @3r
-  SUBSUU_S          011110 011.. ..... ..... .....  010001  @3r
-  ASUB_S            011110 100.. ..... ..... .....  010001  @3r
-  ASUB_U            011110 101.. ..... ..... .....  010001  @3r
-
-  MULV              011110 000.. ..... ..... .....  010010  @3r
-  MADDV             011110 001.. ..... ..... .....  010010  @3r
-  MSUBV             011110 010.. ..... ..... .....  010010  @3r
-  DIV_S             011110 100.. ..... ..... .....  010010  @3r
-  DIV_U             011110 101.. ..... ..... .....  010010  @3r
-  MOD_S             011110 110.. ..... ..... .....  010010  @3r
-  MOD_U             011110 111.. ..... ..... .....  010010  @3r
-
-  DOTP_S            011110 000.. ..... ..... .....  010011  @3r
-  DOTP_U            011110 001.. ..... ..... .....  010011  @3r
-  DPADD_S           011110 010.. ..... ..... .....  010011  @3r
-  DPADD_U           011110 011.. ..... ..... .....  010011  @3r
-  DPSUB_S           011110 100.. ..... ..... .....  010011  @3r
-  DPSUB_U           011110 101.. ..... ..... .....  010011  @3r
-
-  SLD               011110 000 .. ..... ..... ..... 010100  @3r
-  SPLAT             011110 001 .. ..... ..... ..... 010100  @3r
-  PCKEV             011110 010 .. ..... ..... ..... 010100  @3r
-  PCKOD             011110 011 .. ..... ..... ..... 010100  @3r
-  ILVL              011110 100 .. ..... ..... ..... 010100  @3r
-  ILVR              011110 101 .. ..... ..... ..... 010100  @3r
-  ILVEV             011110 110 .. ..... ..... ..... 010100  @3r
-  ILVOD             011110 111 .. ..... ..... ..... 010100  @3r
-
-  VSHF              011110 000 .. ..... ..... ..... 010101  @3r
-  SRAR              011110 001 .. ..... ..... ..... 010101  @3r
-  SRLR              011110 010 .. ..... ..... ..... 010101  @3r
-  HADD_S            011110 100.. ..... ..... .....  010101  @3r
-  HADD_U            011110 101.. ..... ..... .....  010101  @3r
-  HSUB_S            011110 110.. ..... ..... .....  010101  @3r
-  HSUB_U            011110 111.. ..... ..... .....  010101  @3r
-
-  {
-    CTCMSA          011110 0000111110  ..... .....  011001  @elm
-    SLDI            011110 0000 ...... ..... .....  011001  @elm_df
-  }
-  {
-    CFCMSA          011110 0001111110  ..... .....  011001  @elm
-    SPLATI          011110 0001 ...... ..... .....  011001  @elm_df
-  }
-  {
-    MOVE_V          011110 0010111110  ..... .....  011001  @elm
-    COPY_S          011110 0010 ...... ..... .....  011001  @elm_df
-  }
-  COPY_U            011110 0011 ...... ..... .....  011001  @elm_df
-  INSERT            011110 0100 ...... ..... .....  011001  @elm_df
-  INSVE             011110 0101 ...... ..... .....  011001  @elm_df
-
-  FCAF              011110 0000 . ..... ..... ..... 011010  @3rf
-  FCUN              011110 0001 . ..... ..... ..... 011010  @3rf
-  FCEQ              011110 0010 . ..... ..... ..... 011010  @3rf
-  FCUEQ             011110 0011 . ..... ..... ..... 011010  @3rf
-  FCLT              011110 0100 . ..... ..... ..... 011010  @3rf
-  FCULT             011110 0101 . ..... ..... ..... 011010  @3rf
-  FCLE              011110 0110 . ..... ..... ..... 011010  @3rf
-  FCULE             011110 0111 . ..... ..... ..... 011010  @3rf
-  FSAF              011110 1000 . ..... ..... ..... 011010  @3rf
-  FSUN              011110 1001 . ..... ..... ..... 011010  @3rf
-  FSEQ              011110 1010 . ..... ..... ..... 011010  @3rf
-  FSUEQ             011110 1011 . ..... ..... ..... 011010  @3rf
-  FSLT              011110 1100 . ..... ..... ..... 011010  @3rf
-  FSULT             011110 1101 . ..... ..... ..... 011010  @3rf
-  FSLE              011110 1110 . ..... ..... ..... 011010  @3rf
-  FSULE             011110 1111 . ..... ..... ..... 011010  @3rf
-
-  FADD              011110 0000 . ..... ..... ..... 011011  @3rf
-  FSUB              011110 0001 . ..... ..... ..... 011011  @3rf
-  FMUL              011110 0010 . ..... ..... ..... 011011  @3rf
-  FDIV              011110 0011 . ..... ..... ..... 011011  @3rf
-  FMADD             011110 0100 . ..... ..... ..... 011011  @3rf
-  FMSUB             011110 0101 . ..... ..... ..... 011011  @3rf
-  FEXP2             011110 0111 . ..... ..... ..... 011011  @3rf
-  FEXDO             011110 1000 . ..... ..... ..... 011011  @3rf
-  FTQ               011110 1010 . ..... ..... ..... 011011  @3rf
-  FMIN              011110 1100 . ..... ..... ..... 011011  @3rf
-  FMIN_A            011110 1101 . ..... ..... ..... 011011  @3rf
-  FMAX              011110 1110 . ..... ..... ..... 011011  @3rf
-  FMAX_A            011110 1111 . ..... ..... ..... 011011  @3rf
-
-  FCOR              011110 0001 . ..... ..... ..... 011100  @3rf
-  FCUNE             011110 0010 . ..... ..... ..... 011100  @3rf
-  FCNE              011110 0011 . ..... ..... ..... 011100  @3rf
-  MUL_Q             011110 0100 . ..... ..... ..... 011100  @3rf
-  MADD_Q            011110 0101 . ..... ..... ..... 011100  @3rf
-  MSUB_Q            011110 0110 . ..... ..... ..... 011100  @3rf
-  FSOR              011110 1001 . ..... ..... ..... 011100  @3rf
-  FSUNE             011110 1010 . ..... ..... ..... 011100  @3rf
-  FSNE              011110 1011 . ..... ..... ..... 011100  @3rf
-  MULR_Q            011110 1100 . ..... ..... ..... 011100  @3rf
-  MADDR_Q           011110 1101 . ..... ..... ..... 011100  @3rf
-  MSUBR_Q           011110 1110 . ..... ..... ..... 011100  @3rf
-
-  AND_V             011110 00000 ..... ..... .....  011110  @vec
-  OR_V              011110 00001 ..... ..... .....  011110  @vec
-  NOR_V             011110 00010 ..... ..... .....  011110  @vec
-  XOR_V             011110 00011 ..... ..... .....  011110  @vec
-  BMNZ_V            011110 00100 ..... ..... .....  011110  @vec
-  BMZ_V             011110 00101 ..... ..... .....  011110  @vec
-  BSEL_V            011110 00110 ..... ..... .....  011110  @vec
-  FILL              011110 11000000 .. ..... .....  011110  @2r
-  PCNT              011110 11000001 .. ..... .....  011110  @2r
-  NLOC              011110 11000010 .. ..... .....  011110  @2r
-  NLZC              011110 11000011 .. ..... .....  011110  @2r
-  FCLASS            011110 110010000 . ..... .....  011110  @2rf
-  FTRUNC_S          011110 110010001 . ..... .....  011110  @2rf
-  FTRUNC_U          011110 110010010 . ..... .....  011110  @2rf
-  FSQRT             011110 110010011 . ..... .....  011110  @2rf
-  FRSQRT            011110 110010100 . ..... .....  011110  @2rf
-  FRCP              011110 110010101 . ..... .....  011110  @2rf
-  FRINT             011110 110010110 . ..... .....  011110  @2rf
-  FLOG2             011110 110010111 . ..... .....  011110  @2rf
-  FEXUPL            011110 110011000 . ..... .....  011110  @2rf
-  FEXUPR            011110 110011001 . ..... .....  011110  @2rf
-  FFQL              011110 110011010 . ..... .....  011110  @2rf
-  FFQR              011110 110011011 . ..... .....  011110  @2rf
-  FTINT_S           011110 110011100 . ..... .....  011110  @2rf
-  FTINT_U           011110 110011101 . ..... .....  011110  @2rf
-  FFINT_S           011110 110011110 . ..... .....  011110  @2rf
-  FFINT_U           011110 110011111 . ..... .....  011110  @2rf
-
-  LD                011110 .......... ..... .....   1000 .. @ldst
-  ST                011110 .......... ..... .....   1001 .. @ldst
+  CTCMSA            011110 0000111110  ..... .....  011001  @elm
+  SLDI              011110 0000 ...... ..... .....  011001  @elm_df
 }
+{
+  CFCMSA            011110 0001111110  ..... .....  011001  @elm
+  SPLATI            011110 0001 ...... ..... .....  011001  @elm_df
+}
+{
+  MOVE_V            011110 0010111110  ..... .....  011001  @elm
+  COPY_S            011110 0010 ...... ..... .....  011001  @elm_df
+}
+COPY_U              011110 0011 ...... ..... .....  011001  @elm_df
+INSERT              011110 0100 ...... ..... .....  011001  @elm_df
+INSVE               011110 0101 ...... ..... .....  011001  @elm_df
+
+FCAF                011110 0000 . ..... ..... ..... 011010  @3rf
+FCUN                011110 0001 . ..... ..... ..... 011010  @3rf
+FCEQ                011110 0010 . ..... ..... ..... 011010  @3rf
+FCUEQ               011110 0011 . ..... ..... ..... 011010  @3rf
+FCLT                011110 0100 . ..... ..... ..... 011010  @3rf
+FCULT               011110 0101 . ..... ..... ..... 011010  @3rf
+FCLE                011110 0110 . ..... ..... ..... 011010  @3rf
+FCULE               011110 0111 . ..... ..... ..... 011010  @3rf
+FSAF                011110 1000 . ..... ..... ..... 011010  @3rf
+FSUN                011110 1001 . ..... ..... ..... 011010  @3rf
+FSEQ                011110 1010 . ..... ..... ..... 011010  @3rf
+FSUEQ               011110 1011 . ..... ..... ..... 011010  @3rf
+FSLT                011110 1100 . ..... ..... ..... 011010  @3rf
+FSULT               011110 1101 . ..... ..... ..... 011010  @3rf
+FSLE                011110 1110 . ..... ..... ..... 011010  @3rf
+FSULE               011110 1111 . ..... ..... ..... 011010  @3rf
+
+FADD                011110 0000 . ..... ..... ..... 011011  @3rf
+FSUB                011110 0001 . ..... ..... ..... 011011  @3rf
+FMUL                011110 0010 . ..... ..... ..... 011011  @3rf
+FDIV                011110 0011 . ..... ..... ..... 011011  @3rf
+FMADD               011110 0100 . ..... ..... ..... 011011  @3rf
+FMSUB               011110 0101 . ..... ..... ..... 011011  @3rf
+FEXP2               011110 0111 . ..... ..... ..... 011011  @3rf
+FEXDO               011110 1000 . ..... ..... ..... 011011  @3rf
+FTQ                 011110 1010 . ..... ..... ..... 011011  @3rf
+FMIN                011110 1100 . ..... ..... ..... 011011  @3rf
+FMIN_A              011110 1101 . ..... ..... ..... 011011  @3rf
+FMAX                011110 1110 . ..... ..... ..... 011011  @3rf
+FMAX_A              011110 1111 . ..... ..... ..... 011011  @3rf
+
+FCOR                011110 0001 . ..... ..... ..... 011100  @3rf
+FCUNE               011110 0010 . ..... ..... ..... 011100  @3rf
+FCNE                011110 0011 . ..... ..... ..... 011100  @3rf
+MUL_Q               011110 0100 . ..... ..... ..... 011100  @3rf
+MADD_Q              011110 0101 . ..... ..... ..... 011100  @3rf
+MSUB_Q              011110 0110 . ..... ..... ..... 011100  @3rf
+FSOR                011110 1001 . ..... ..... ..... 011100  @3rf
+FSUNE               011110 1010 . ..... ..... ..... 011100  @3rf
+FSNE                011110 1011 . ..... ..... ..... 011100  @3rf
+MULR_Q              011110 1100 . ..... ..... ..... 011100  @3rf
+MADDR_Q             011110 1101 . ..... ..... ..... 011100  @3rf
+MSUBR_Q             011110 1110 . ..... ..... ..... 011100  @3rf
+
+AND_V               011110 00000 ..... ..... .....  011110  @vec
+OR_V                011110 00001 ..... ..... .....  011110  @vec
+NOR_V               011110 00010 ..... ..... .....  011110  @vec
+XOR_V               011110 00011 ..... ..... .....  011110  @vec
+BMNZ_V              011110 00100 ..... ..... .....  011110  @vec
+BMZ_V               011110 00101 ..... ..... .....  011110  @vec
+BSEL_V              011110 00110 ..... ..... .....  011110  @vec
+FILL                011110 11000000 .. ..... .....  011110  @2r
+PCNT                011110 11000001 .. ..... .....  011110  @2r
+NLOC                011110 11000010 .. ..... .....  011110  @2r
+NLZC                011110 11000011 .. ..... .....  011110  @2r
+FCLASS              011110 110010000 . ..... .....  011110  @2rf
+FTRUNC_S            011110 110010001 . ..... .....  011110  @2rf
+FTRUNC_U            011110 110010010 . ..... .....  011110  @2rf
+FSQRT               011110 110010011 . ..... .....  011110  @2rf
+FRSQRT              011110 110010100 . ..... .....  011110  @2rf
+FRCP                011110 110010101 . ..... .....  011110  @2rf
+FRINT               011110 110010110 . ..... .....  011110  @2rf
+FLOG2               011110 110010111 . ..... .....  011110  @2rf
+FEXUPL              011110 110011000 . ..... .....  011110  @2rf
+FEXUPR              011110 110011001 . ..... .....  011110  @2rf
+FFQL                011110 110011010 . ..... .....  011110  @2rf
+FFQR                011110 110011011 . ..... .....  011110  @2rf
+FTINT_S             011110 110011100 . ..... .....  011110  @2rf
+FTINT_U             011110 110011101 . ..... .....  011110  @2rf
+FFINT_S             011110 110011110 . ..... .....  011110  @2rf
+FFINT_U             011110 110011111 . ..... .....  011110  @2rf
+
+LD                  011110 .......... ..... .....   1000 .. @ldst
+ST                  011110 .......... ..... .....   1001 .. @ldst
-- 
2.31.1



  parent reply	other threads:[~2021-10-23 22:16 UTC|newest]

Thread overview: 78+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 01/33] tests/tcg: Fix some targets default cross compiler path Philippe Mathieu-Daudé
2021-10-23 23:24   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 02/33] target/mips: Fix MSA MADDV.B opcode Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 03/33] target/mips: Fix MSA MSUBV.B opcode Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 04/33] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation Philippe Mathieu-Daudé
2021-10-27 10:38   ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 05/33] target/mips: Have check_msa_access() return a boolean Philippe Mathieu-Daudé
2021-10-24  1:02   ` Richard Henderson
2021-10-24 12:48     ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 06/33] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum Philippe Mathieu-Daudé
2021-10-24  1:03   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 07/33] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v Philippe Mathieu-Daudé
2021-10-24  1:05   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 08/33] target/mips: Convert MSA LDI opcode to decodetree Philippe Mathieu-Daudé
2021-10-24  1:53   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 09/33] target/mips: Introduce generic TRANS_CHECK() for decodetree helpers Philippe Mathieu-Daudé
2021-10-24  1:58   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 10/33] target/mips: Extract df_extract() helper Philippe Mathieu-Daudé
2021-10-24  2:26   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 11/33] target/mips: Convert MSA I5 instruction format to decodetree Philippe Mathieu-Daudé
2021-10-24  2:10   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 12/33] target/mips: Convert MSA BIT " Philippe Mathieu-Daudé
2021-10-24  2:45   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 13/33] target/mips: Convert MSA SHF opcode " Philippe Mathieu-Daudé
2021-10-24  3:40   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 14/33] target/mips: Convert MSA I8 instruction format " Philippe Mathieu-Daudé
2021-10-24  3:45   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 15/33] target/mips: Convert MSA load/store " Philippe Mathieu-Daudé
2021-10-24  4:53   ` Richard Henderson
2021-10-24 11:18     ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 16/33] target/mips: Convert MSA 2RF " Philippe Mathieu-Daudé
2021-10-24  5:01   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 17/33] target/mips: Convert MSA FILL opcode " Philippe Mathieu-Daudé
2021-10-24  5:04   ` Richard Henderson
2021-10-24 16:44     ` Philippe Mathieu-Daudé
2021-10-24 17:26       ` Richard Henderson
2021-10-25 16:43         ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 18/33] target/mips: Convert MSA 2R instruction format " Philippe Mathieu-Daudé
2021-10-24  5:14   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 19/33] target/mips: Convert MSA VEC " Philippe Mathieu-Daudé
2021-10-24  5:17   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 20/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Philippe Mathieu-Daudé
2021-10-24 17:37   ` Richard Henderson
2021-10-24 17:42     ` Richard Henderson
2021-10-23 21:47 ` [PATCH 21/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) Philippe Mathieu-Daudé
2021-10-24 17:42   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 22/33] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) Philippe Mathieu-Daudé
2021-10-24 17:51   ` Richard Henderson
2021-10-24 17:52   ` Richard Henderson
2021-10-24 18:57     ` Philippe Mathieu-Daudé
2021-10-24 20:27       ` Richard Henderson
2021-10-23 21:47 ` [PATCH 23/33] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Philippe Mathieu-Daudé
2021-10-24 17:55   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 24/33] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) Philippe Mathieu-Daudé
2021-10-24 18:09   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 25/33] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) Philippe Mathieu-Daudé
2021-10-24 18:12   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 26/33] target/mips: Convert MSA ELM instruction format to decodetree Philippe Mathieu-Daudé
2021-10-24 20:52   ` Richard Henderson
2021-10-27 17:27     ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 27/33] target/mips: Convert MSA COPY_U opcode " Philippe Mathieu-Daudé
2021-10-24 21:01   ` Richard Henderson
2021-10-27 17:40     ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 28/33] target/mips: Convert MSA COPY_S and INSERT opcodes " Philippe Mathieu-Daudé
2021-10-24 21:02   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 29/33] target/mips: Convert MSA MOVE.V opcode " Philippe Mathieu-Daudé
2021-10-24 21:09   ` Richard Henderson
2021-10-23 21:48 ` [PATCH 30/33] target/mips: Convert CFCMSA and CTCMSA opcodes " Philippe Mathieu-Daudé
2021-10-24 21:15   ` Richard Henderson
2021-10-23 21:48 ` [PATCH 31/33] target/mips: Remove generic MSA opcode Philippe Mathieu-Daudé
2021-10-24 21:16   ` Richard Henderson
2021-10-23 21:48 ` Philippe Mathieu-Daudé [this message]
2021-10-24 21:17   ` [PATCH 32/33] target/mips: Remove one MSA unnecessary decodetree overlap group Richard Henderson
2021-10-23 21:48 ` [PATCH 33/33] target/mips: Adjust style in msa_translate_init() Philippe Mathieu-Daudé
2021-10-24 21:18   ` Richard Henderson
2021-10-24 18:26 ` [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Jiaxun Yang
2021-10-24 19:01   ` Philippe Mathieu-Daudé

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