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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
	"Luis Pires" <luis.pires@eldorado.org.br>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PATCH 25/33] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4)
Date: Sat, 23 Oct 2021 23:47:55 +0200	[thread overview]
Message-ID: <20211023214803.522078-26-f4bug@amsat.org> (raw)
In-Reply-To: <20211023214803.522078-1-f4bug@amsat.org>

Convert 3-register operations to decodetree.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      |  53 ++
 target/mips/tcg/msa_translate.c | 916 ++------------------------------
 2 files changed, 106 insertions(+), 863 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 1d6fd86ef3d..3d0d9a52675 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -80,9 +80,54 @@ BNZ                 010001 111 .. ..... ................    @bz
   SRARI             011110 010 ....... ..... .....  001010  @bit
   SRLRI             011110 011 ....... ..... .....  001010  @bit
 
+  SLL               011110 000.. ..... ..... .....  001101  @3r
+  SRA               011110 001.. ..... ..... .....  001101  @3r
+  SRL               011110 010.. ..... ..... .....  001101  @3r
+  BCLR              011110 011.. ..... ..... .....  001101  @3r
+  BSET              011110 100.. ..... ..... .....  001101  @3r
+  BNEG              011110 101.. ..... ..... .....  001101  @3r
   BINSL             011110 110.. ..... ..... .....  001101  @3r
   BINSR             011110 111.. ..... ..... .....  001101  @3r
 
+  ADDV              011110 000.. ..... ..... .....  001110  @3r
+  SUBV              011110 001.. ..... ..... .....  001110  @3r
+  MAX_S             011110 010.. ..... ..... .....  001110  @3r
+  MAX_U             011110 011.. ..... ..... .....  001110  @3r
+  MIN_S             011110 100.. ..... ..... .....  001110  @3r
+  MIN_U             011110 101.. ..... ..... .....  001110  @3r
+  MAX_A             011110 110.. ..... ..... .....  001110  @3r
+  MIN_A             011110 111.. ..... ..... .....  001110  @3r
+
+  CEQ               011110 000.. ..... ..... .....  001111  @3r
+  CLT_S             011110 010.. ..... ..... .....  001111  @3r
+  CLT_U             011110 011.. ..... ..... .....  001111  @3r
+  CLE_S             011110 100.. ..... ..... .....  001111  @3r
+  CLE_U             011110 101.. ..... ..... .....  001111  @3r
+
+  ADD_A             011110 000.. ..... ..... .....  010000  @3r
+  ADDS_A            011110 001.. ..... ..... .....  010000  @3r
+  ADDS_S            011110 010.. ..... ..... .....  010000  @3r
+  ADDS_U            011110 011.. ..... ..... .....  010000  @3r
+  AVE_S             011110 100.. ..... ..... .....  010000  @3r
+  AVE_U             011110 101.. ..... ..... .....  010000  @3r
+  AVER_S            011110 110.. ..... ..... .....  010000  @3r
+  AVER_U            011110 111.. ..... ..... .....  010000  @3r
+
+  SUBS_S            011110 000.. ..... ..... .....  010001  @3r
+  SUBS_U            011110 001.. ..... ..... .....  010001  @3r
+  SUBSUS_U          011110 010.. ..... ..... .....  010001  @3r
+  SUBSUU_S          011110 011.. ..... ..... .....  010001  @3r
+  ASUB_S            011110 100.. ..... ..... .....  010001  @3r
+  ASUB_U            011110 101.. ..... ..... .....  010001  @3r
+
+  MULV              011110 000.. ..... ..... .....  010010  @3r
+  MADDV             011110 001.. ..... ..... .....  010010  @3r
+  MSUBV             011110 010.. ..... ..... .....  010010  @3r
+  DIV_S             011110 100.. ..... ..... .....  010010  @3r
+  DIV_U             011110 101.. ..... ..... .....  010010  @3r
+  MOD_S             011110 110.. ..... ..... .....  010010  @3r
+  MOD_U             011110 111.. ..... ..... .....  010010  @3r
+
   DOTP_S            011110 000.. ..... ..... .....  010011  @3r
   DOTP_U            011110 001.. ..... ..... .....  010011  @3r
   DPADD_S           011110 010.. ..... ..... .....  010011  @3r
@@ -92,8 +137,16 @@ BNZ                 010001 111 .. ..... ................    @bz
 
   SLD               011110 000 .. ..... ..... ..... 010100  @3r
   SPLAT             011110 001 .. ..... ..... ..... 010100  @3r
+  PCKEV             011110 010 .. ..... ..... ..... 010100  @3r
+  PCKOD             011110 011 .. ..... ..... ..... 010100  @3r
+  ILVL              011110 100 .. ..... ..... ..... 010100  @3r
+  ILVR              011110 101 .. ..... ..... ..... 010100  @3r
+  ILVEV             011110 110 .. ..... ..... ..... 010100  @3r
+  ILVOD             011110 111 .. ..... ..... ..... 010100  @3r
 
   VSHF              011110 000 .. ..... ..... ..... 010101  @3r
+  SRAR              011110 001 .. ..... ..... ..... 010101  @3r
+  SRLR              011110 010 .. ..... ..... ..... 010101  @3r
   HADD_S            011110 100.. ..... ..... .....  010101  @3r
   HADD_U            011110 101.. ..... ..... .....  010101  @3r
   HSUB_S            011110 110.. ..... ..... .....  010101  @3r
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 1b69ec149a5..7813c126069 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -24,69 +24,10 @@
 
 #define MASK_MSA_MINOR(op)          (MASK_OP_MAJOR(op) | (op & 0x3F))
 enum {
-    OPC_MSA_3R_0D   = 0x0D | OPC_MSA,
-    OPC_MSA_3R_0E   = 0x0E | OPC_MSA,
-    OPC_MSA_3R_0F   = 0x0F | OPC_MSA,
-    OPC_MSA_3R_10   = 0x10 | OPC_MSA,
-    OPC_MSA_3R_11   = 0x11 | OPC_MSA,
-    OPC_MSA_3R_12   = 0x12 | OPC_MSA,
-    OPC_MSA_3R_13   = 0x13 | OPC_MSA,
-    OPC_MSA_3R_14   = 0x14 | OPC_MSA,
-    OPC_MSA_3R_15   = 0x15 | OPC_MSA,
     OPC_MSA_ELM     = 0x19 | OPC_MSA,
 };
 
 enum {
-    /* 3R instruction df(bits 22..21) = _b, _h, _w, d */
-    OPC_SLL_df      = (0x0 << 23) | OPC_MSA_3R_0D,
-    OPC_ADDV_df     = (0x0 << 23) | OPC_MSA_3R_0E,
-    OPC_CEQ_df      = (0x0 << 23) | OPC_MSA_3R_0F,
-    OPC_ADD_A_df    = (0x0 << 23) | OPC_MSA_3R_10,
-    OPC_SUBS_S_df   = (0x0 << 23) | OPC_MSA_3R_11,
-    OPC_MULV_df     = (0x0 << 23) | OPC_MSA_3R_12,
-    OPC_SRA_df      = (0x1 << 23) | OPC_MSA_3R_0D,
-    OPC_SUBV_df     = (0x1 << 23) | OPC_MSA_3R_0E,
-    OPC_ADDS_A_df   = (0x1 << 23) | OPC_MSA_3R_10,
-    OPC_SUBS_U_df   = (0x1 << 23) | OPC_MSA_3R_11,
-    OPC_MADDV_df    = (0x1 << 23) | OPC_MSA_3R_12,
-    OPC_SRAR_df     = (0x1 << 23) | OPC_MSA_3R_15,
-    OPC_SRL_df      = (0x2 << 23) | OPC_MSA_3R_0D,
-    OPC_MAX_S_df    = (0x2 << 23) | OPC_MSA_3R_0E,
-    OPC_CLT_S_df    = (0x2 << 23) | OPC_MSA_3R_0F,
-    OPC_ADDS_S_df   = (0x2 << 23) | OPC_MSA_3R_10,
-    OPC_SUBSUS_U_df = (0x2 << 23) | OPC_MSA_3R_11,
-    OPC_MSUBV_df    = (0x2 << 23) | OPC_MSA_3R_12,
-    OPC_PCKEV_df    = (0x2 << 23) | OPC_MSA_3R_14,
-    OPC_SRLR_df     = (0x2 << 23) | OPC_MSA_3R_15,
-    OPC_BCLR_df     = (0x3 << 23) | OPC_MSA_3R_0D,
-    OPC_MAX_U_df    = (0x3 << 23) | OPC_MSA_3R_0E,
-    OPC_CLT_U_df    = (0x3 << 23) | OPC_MSA_3R_0F,
-    OPC_ADDS_U_df   = (0x3 << 23) | OPC_MSA_3R_10,
-    OPC_SUBSUU_S_df = (0x3 << 23) | OPC_MSA_3R_11,
-    OPC_PCKOD_df    = (0x3 << 23) | OPC_MSA_3R_14,
-    OPC_BSET_df     = (0x4 << 23) | OPC_MSA_3R_0D,
-    OPC_MIN_S_df    = (0x4 << 23) | OPC_MSA_3R_0E,
-    OPC_CLE_S_df    = (0x4 << 23) | OPC_MSA_3R_0F,
-    OPC_AVE_S_df    = (0x4 << 23) | OPC_MSA_3R_10,
-    OPC_ASUB_S_df   = (0x4 << 23) | OPC_MSA_3R_11,
-    OPC_DIV_S_df    = (0x4 << 23) | OPC_MSA_3R_12,
-    OPC_ILVL_df     = (0x4 << 23) | OPC_MSA_3R_14,
-    OPC_BNEG_df     = (0x5 << 23) | OPC_MSA_3R_0D,
-    OPC_MIN_U_df    = (0x5 << 23) | OPC_MSA_3R_0E,
-    OPC_CLE_U_df    = (0x5 << 23) | OPC_MSA_3R_0F,
-    OPC_AVE_U_df    = (0x5 << 23) | OPC_MSA_3R_10,
-    OPC_ASUB_U_df   = (0x5 << 23) | OPC_MSA_3R_11,
-    OPC_DIV_U_df    = (0x5 << 23) | OPC_MSA_3R_12,
-    OPC_ILVR_df     = (0x5 << 23) | OPC_MSA_3R_14,
-    OPC_MAX_A_df    = (0x6 << 23) | OPC_MSA_3R_0E,
-    OPC_AVER_S_df   = (0x6 << 23) | OPC_MSA_3R_10,
-    OPC_MOD_S_df    = (0x6 << 23) | OPC_MSA_3R_12,
-    OPC_ILVEV_df    = (0x6 << 23) | OPC_MSA_3R_14,
-    OPC_MIN_A_df    = (0x7 << 23) | OPC_MSA_3R_0E,
-    OPC_AVER_U_df   = (0x7 << 23) | OPC_MSA_3R_10,
-    OPC_MOD_U_df    = (0x7 << 23) | OPC_MSA_3R_12,
-    OPC_ILVOD_df    = (0x7 << 23) | OPC_MSA_3R_14,
-
     /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
     OPC_SLDI_df     = (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM,
     OPC_CTCMSA      = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
@@ -516,9 +457,54 @@ static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a,
     return true;
 }
 
+TRANS_DF_E(SLL,         trans_msa_3r,    gen_helper_msa_sll);
+TRANS_DF_E(SRA,         trans_msa_3r,    gen_helper_msa_sra);
+TRANS_DF_E(SRL,         trans_msa_3r,    gen_helper_msa_srl);
+TRANS_DF_E(BCLR,        trans_msa_3r,    gen_helper_msa_bclr);
+TRANS_DF_E(BSET,        trans_msa_3r,    gen_helper_msa_bset);
+TRANS_DF_E(BNEG,        trans_msa_3r,    gen_helper_msa_bneg);
 TRANS_DF_E(BINSL,       trans_msa_3r,    gen_helper_msa_binsl);
 TRANS_DF_E(BINSR,       trans_msa_3r,    gen_helper_msa_binsr);
 
+TRANS_DF_E(ADDV,        trans_msa_3r,    gen_helper_msa_addv);
+TRANS_DF_E(SUBV,        trans_msa_3r,    gen_helper_msa_subv);
+TRANS_DF_E(MAX_S,       trans_msa_3r,    gen_helper_msa_max_s);
+TRANS_DF_E(MAX_U,       trans_msa_3r,    gen_helper_msa_max_u);
+TRANS_DF_E(MIN_S,       trans_msa_3r,    gen_helper_msa_min_s);
+TRANS_DF_E(MIN_U,       trans_msa_3r,    gen_helper_msa_min_u);
+TRANS_DF_E(MAX_A,       trans_msa_3r,    gen_helper_msa_max_a);
+TRANS_DF_E(MIN_A,       trans_msa_3r,    gen_helper_msa_min_a);
+
+TRANS_DF_E(CEQ,         trans_msa_3r,    gen_helper_msa_ceq);
+TRANS_DF_E(CLT_S,       trans_msa_3r,    gen_helper_msa_clt_s);
+TRANS_DF_E(CLT_U,       trans_msa_3r,    gen_helper_msa_clt_u);
+TRANS_DF_E(CLE_S,       trans_msa_3r,    gen_helper_msa_cle_s);
+TRANS_DF_E(CLE_U,       trans_msa_3r,    gen_helper_msa_cle_u);
+
+TRANS_DF_E(ADD_A,       trans_msa_3r,    gen_helper_msa_add_a);
+TRANS_DF_E(ADDS_A,      trans_msa_3r,    gen_helper_msa_adds_a);
+TRANS_DF_E(ADDS_S,      trans_msa_3r,    gen_helper_msa_adds_s);
+TRANS_DF_E(ADDS_U,      trans_msa_3r,    gen_helper_msa_adds_u);
+TRANS_DF_E(AVE_S,       trans_msa_3r,    gen_helper_msa_ave_s);
+TRANS_DF_E(AVE_U,       trans_msa_3r,    gen_helper_msa_ave_u);
+TRANS_DF_E(AVER_S,      trans_msa_3r,    gen_helper_msa_aver_s);
+TRANS_DF_E(AVER_U,      trans_msa_3r,    gen_helper_msa_aver_u);
+
+TRANS_DF_E(SUBS_S,      trans_msa_3r,    gen_helper_msa_subs_s);
+TRANS_DF_E(SUBS_U,      trans_msa_3r,    gen_helper_msa_subs_u);
+TRANS_DF_E(SUBSUS_U,    trans_msa_3r,    gen_helper_msa_subsus_u);
+TRANS_DF_E(SUBSUU_S,    trans_msa_3r,    gen_helper_msa_subsuu_s);
+TRANS_DF_E(ASUB_S,      trans_msa_3r,    gen_helper_msa_asub_s);
+TRANS_DF_E(ASUB_U,      trans_msa_3r,    gen_helper_msa_asub_u);
+
+TRANS_DF_E(MULV,        trans_msa_3r,    gen_helper_msa_mulv);
+TRANS_DF_E(MADDV,       trans_msa_3r,    gen_helper_msa_maddv);
+TRANS_DF_E(MSUBV,       trans_msa_3r,    gen_helper_msa_msubv);
+TRANS_DF_E(DIV_S,       trans_msa_3r,    gen_helper_msa_div_s);
+TRANS_DF_E(DIV_U,       trans_msa_3r,    gen_helper_msa_div_u);
+TRANS_DF_E(MOD_S,       trans_msa_3r,    gen_helper_msa_mod_s);
+TRANS_DF_E(MOD_U,       trans_msa_3r,    gen_helper_msa_mod_u);
+
 TRANS_DF_B(DOTP_S,      trans_msa_3r,    gen_helper_msa_dotp_s);
 TRANS_DF_B(DOTP_U,      trans_msa_3r,    gen_helper_msa_dotp_u);
 TRANS_DF_B(DPADD_S,     trans_msa_3r,    gen_helper_msa_dpadd_s);
@@ -528,806 +514,21 @@ TRANS_DF_B(DPSUB_U,     trans_msa_3r,    gen_helper_msa_dpsub_u);
 
 TRANS_MSA(SLD,          trans_msa_3r_df, gen_helper_msa_sld_df);
 TRANS_MSA(SPLAT,        trans_msa_3r_df, gen_helper_msa_splat_df);
+TRANS_DF_E(PCKEV,       trans_msa_3r,    gen_helper_msa_pckev);
+TRANS_DF_E(PCKOD,       trans_msa_3r,    gen_helper_msa_pckod);
+TRANS_DF_E(ILVL,        trans_msa_3r,    gen_helper_msa_ilvl);
+TRANS_DF_E(ILVR,        trans_msa_3r,    gen_helper_msa_ilvr);
+TRANS_DF_E(ILVEV,       trans_msa_3r,    gen_helper_msa_ilvev);
+TRANS_DF_E(ILVOD,       trans_msa_3r,    gen_helper_msa_ilvod);
 
 TRANS_MSA(VSHF,         trans_msa_3r_df, gen_helper_msa_vshf_df);
+TRANS_DF_E(SRAR,        trans_msa_3r,    gen_helper_msa_srar);
+TRANS_DF_E(SRLR,        trans_msa_3r,    gen_helper_msa_srlr);
 TRANS_DF_B(HADD_S,      trans_msa_3r,    gen_helper_msa_hadd_s);
 TRANS_DF_B(HADD_U,      trans_msa_3r,    gen_helper_msa_hadd_u);
 TRANS_DF_B(HSUB_S,      trans_msa_3r,    gen_helper_msa_hsub_s);
 TRANS_DF_B(HSUB_U,      trans_msa_3r,    gen_helper_msa_hsub_u);
 
-static void gen_msa_3r(DisasContext *ctx)
-{
-#define MASK_MSA_3R(op)    (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
-    uint8_t df = (ctx->opcode >> 21) & 0x3;
-    uint8_t wt = (ctx->opcode >> 16) & 0x1f;
-    uint8_t ws = (ctx->opcode >> 11) & 0x1f;
-    uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-
-    TCGv_i32 tdf = tcg_const_i32(df);
-    TCGv_i32 twd = tcg_const_i32(wd);
-    TCGv_i32 tws = tcg_const_i32(ws);
-    TCGv_i32 twt = tcg_const_i32(wt);
-
-    switch (MASK_MSA_3R(ctx->opcode)) {
-    case OPC_BCLR_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_bclr_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_bclr_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_bclr_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_bclr_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_BNEG_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_bneg_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_bneg_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_bneg_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_bneg_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_BSET_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_bset_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_bset_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_bset_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_bset_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_ADD_A_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_add_a_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_add_a_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_add_a_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_add_a_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_ADDS_A_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_adds_a_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_adds_a_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_adds_a_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_adds_a_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_ADDS_S_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_adds_s_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_adds_s_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_adds_s_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_adds_s_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_ADDS_U_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_adds_u_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_adds_u_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_adds_u_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_adds_u_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_ADDV_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_addv_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_addv_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_addv_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_addv_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_AVE_S_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_ave_s_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_ave_s_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_ave_s_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_ave_s_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_AVE_U_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_ave_u_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_ave_u_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_ave_u_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_ave_u_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_AVER_S_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_aver_s_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_aver_s_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_aver_s_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_aver_s_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_AVER_U_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_aver_u_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_aver_u_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_aver_u_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_aver_u_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_CEQ_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_ceq_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_ceq_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_ceq_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_ceq_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_CLE_S_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_cle_s_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_cle_s_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_cle_s_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_cle_s_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_CLE_U_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_cle_u_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_cle_u_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_cle_u_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_cle_u_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_CLT_S_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_clt_s_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_clt_s_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_clt_s_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_clt_s_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_CLT_U_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_clt_u_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_clt_u_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_clt_u_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_clt_u_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_DIV_S_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_div_s_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_div_s_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_div_s_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_div_s_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_DIV_U_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_div_u_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_div_u_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_div_u_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_div_u_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_MAX_A_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_max_a_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_max_a_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_max_a_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_max_a_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_MAX_S_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_max_s_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_max_s_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_max_s_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_max_s_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_MAX_U_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_max_u_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_max_u_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_max_u_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_max_u_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_MIN_A_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_min_a_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_min_a_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_min_a_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_min_a_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_MIN_S_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_min_s_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_min_s_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_min_s_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_min_s_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_MIN_U_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_min_u_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_min_u_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_min_u_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_min_u_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_MOD_S_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_mod_s_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_mod_s_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_mod_s_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_mod_s_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_MOD_U_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_mod_u_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_mod_u_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_mod_u_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_mod_u_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_MADDV_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_maddv_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_maddv_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_maddv_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_maddv_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_MSUBV_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_msubv_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_msubv_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_msubv_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_msubv_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_ASUB_S_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_asub_s_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_asub_s_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_asub_s_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_asub_s_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_ASUB_U_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_asub_u_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_asub_u_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_asub_u_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_asub_u_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_ILVEV_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_ilvev_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_ilvev_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_ilvev_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_ilvev_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_ILVOD_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_ilvod_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_ilvod_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_ilvod_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_ilvod_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_ILVL_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_ilvl_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_ilvl_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_ilvl_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_ilvl_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_ILVR_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_ilvr_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_ilvr_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_ilvr_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_ilvr_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_PCKEV_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_pckev_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_pckev_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_pckev_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_pckev_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_PCKOD_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_pckod_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_pckod_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_pckod_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_pckod_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_SLL_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_sll_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_sll_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_sll_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_sll_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_SRA_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_sra_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_sra_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_sra_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_sra_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_SRAR_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_srar_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_srar_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_srar_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_srar_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_SRL_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_srl_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_srl_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_srl_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_srl_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_SRLR_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_srlr_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_srlr_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_srlr_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_srlr_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_SUBS_S_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_subs_s_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_subs_s_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_subs_s_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_subs_s_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_MULV_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_mulv_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_mulv_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_mulv_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_mulv_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_SUBV_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_subv_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_subv_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_subv_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_subv_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_SUBS_U_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_subs_u_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_subs_u_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_subs_u_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_subs_u_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_SUBSUS_U_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_subsus_u_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_subsus_u_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_subsus_u_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_subsus_u_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    case OPC_SUBSUU_S_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_subsuu_s_b(cpu_env, twd, tws, twt);
-            break;
-        case DF_HALF:
-            gen_helper_msa_subsuu_s_h(cpu_env, twd, tws, twt);
-            break;
-        case DF_WORD:
-            gen_helper_msa_subsuu_s_w(cpu_env, twd, tws, twt);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_subsuu_s_d(cpu_env, twd, tws, twt);
-            break;
-        }
-        break;
-    default:
-        MIPS_INVAL("MSA instruction");
-        gen_reserved_instruction(ctx);
-        break;
-    }
-    tcg_temp_free_i32(twd);
-    tcg_temp_free_i32(tws);
-    tcg_temp_free_i32(twt);
-    tcg_temp_free_i32(tdf);
-}
-
 static void gen_msa_elm_3e(DisasContext *ctx)
 {
 #define MASK_MSA_ELM_DF3E(op)   (MASK_MSA_MINOR(op) | (op & (0x3FF << 16)))
@@ -1684,17 +885,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
     }
 
     switch (MASK_MSA_MINOR(opcode)) {
-    case OPC_MSA_3R_0D:
-    case OPC_MSA_3R_0E:
-    case OPC_MSA_3R_0F:
-    case OPC_MSA_3R_10:
-    case OPC_MSA_3R_11:
-    case OPC_MSA_3R_12:
-    case OPC_MSA_3R_13:
-    case OPC_MSA_3R_14:
-    case OPC_MSA_3R_15:
-        gen_msa_3r(ctx);
-        break;
     case OPC_MSA_ELM:
         gen_msa_elm(ctx);
         break;
-- 
2.31.1



  parent reply	other threads:[~2021-10-23 22:15 UTC|newest]

Thread overview: 78+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 01/33] tests/tcg: Fix some targets default cross compiler path Philippe Mathieu-Daudé
2021-10-23 23:24   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 02/33] target/mips: Fix MSA MADDV.B opcode Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 03/33] target/mips: Fix MSA MSUBV.B opcode Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 04/33] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation Philippe Mathieu-Daudé
2021-10-27 10:38   ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 05/33] target/mips: Have check_msa_access() return a boolean Philippe Mathieu-Daudé
2021-10-24  1:02   ` Richard Henderson
2021-10-24 12:48     ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 06/33] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum Philippe Mathieu-Daudé
2021-10-24  1:03   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 07/33] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v Philippe Mathieu-Daudé
2021-10-24  1:05   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 08/33] target/mips: Convert MSA LDI opcode to decodetree Philippe Mathieu-Daudé
2021-10-24  1:53   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 09/33] target/mips: Introduce generic TRANS_CHECK() for decodetree helpers Philippe Mathieu-Daudé
2021-10-24  1:58   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 10/33] target/mips: Extract df_extract() helper Philippe Mathieu-Daudé
2021-10-24  2:26   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 11/33] target/mips: Convert MSA I5 instruction format to decodetree Philippe Mathieu-Daudé
2021-10-24  2:10   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 12/33] target/mips: Convert MSA BIT " Philippe Mathieu-Daudé
2021-10-24  2:45   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 13/33] target/mips: Convert MSA SHF opcode " Philippe Mathieu-Daudé
2021-10-24  3:40   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 14/33] target/mips: Convert MSA I8 instruction format " Philippe Mathieu-Daudé
2021-10-24  3:45   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 15/33] target/mips: Convert MSA load/store " Philippe Mathieu-Daudé
2021-10-24  4:53   ` Richard Henderson
2021-10-24 11:18     ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 16/33] target/mips: Convert MSA 2RF " Philippe Mathieu-Daudé
2021-10-24  5:01   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 17/33] target/mips: Convert MSA FILL opcode " Philippe Mathieu-Daudé
2021-10-24  5:04   ` Richard Henderson
2021-10-24 16:44     ` Philippe Mathieu-Daudé
2021-10-24 17:26       ` Richard Henderson
2021-10-25 16:43         ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 18/33] target/mips: Convert MSA 2R instruction format " Philippe Mathieu-Daudé
2021-10-24  5:14   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 19/33] target/mips: Convert MSA VEC " Philippe Mathieu-Daudé
2021-10-24  5:17   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 20/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Philippe Mathieu-Daudé
2021-10-24 17:37   ` Richard Henderson
2021-10-24 17:42     ` Richard Henderson
2021-10-23 21:47 ` [PATCH 21/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) Philippe Mathieu-Daudé
2021-10-24 17:42   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 22/33] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) Philippe Mathieu-Daudé
2021-10-24 17:51   ` Richard Henderson
2021-10-24 17:52   ` Richard Henderson
2021-10-24 18:57     ` Philippe Mathieu-Daudé
2021-10-24 20:27       ` Richard Henderson
2021-10-23 21:47 ` [PATCH 23/33] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Philippe Mathieu-Daudé
2021-10-24 17:55   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 24/33] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) Philippe Mathieu-Daudé
2021-10-24 18:09   ` Richard Henderson
2021-10-23 21:47 ` Philippe Mathieu-Daudé [this message]
2021-10-24 18:12   ` [PATCH 25/33] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) Richard Henderson
2021-10-23 21:47 ` [PATCH 26/33] target/mips: Convert MSA ELM instruction format to decodetree Philippe Mathieu-Daudé
2021-10-24 20:52   ` Richard Henderson
2021-10-27 17:27     ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 27/33] target/mips: Convert MSA COPY_U opcode " Philippe Mathieu-Daudé
2021-10-24 21:01   ` Richard Henderson
2021-10-27 17:40     ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 28/33] target/mips: Convert MSA COPY_S and INSERT opcodes " Philippe Mathieu-Daudé
2021-10-24 21:02   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 29/33] target/mips: Convert MSA MOVE.V opcode " Philippe Mathieu-Daudé
2021-10-24 21:09   ` Richard Henderson
2021-10-23 21:48 ` [PATCH 30/33] target/mips: Convert CFCMSA and CTCMSA opcodes " Philippe Mathieu-Daudé
2021-10-24 21:15   ` Richard Henderson
2021-10-23 21:48 ` [PATCH 31/33] target/mips: Remove generic MSA opcode Philippe Mathieu-Daudé
2021-10-24 21:16   ` Richard Henderson
2021-10-23 21:48 ` [PATCH 32/33] target/mips: Remove one MSA unnecessary decodetree overlap group Philippe Mathieu-Daudé
2021-10-24 21:17   ` Richard Henderson
2021-10-23 21:48 ` [PATCH 33/33] target/mips: Adjust style in msa_translate_init() Philippe Mathieu-Daudé
2021-10-24 21:18   ` Richard Henderson
2021-10-24 18:26 ` [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Jiaxun Yang
2021-10-24 19:01   ` Philippe Mathieu-Daudé

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