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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
	"Luis Pires" <luis.pires@eldorado.org.br>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PATCH 18/33] target/mips: Convert MSA 2R instruction format to decodetree
Date: Sat, 23 Oct 2021 23:47:48 +0200	[thread overview]
Message-ID: <20211023214803.522078-19-f4bug@amsat.org> (raw)
In-Reply-To: <20211023214803.522078-1-f4bug@amsat.org>

Convert 2-register operations to decodetree.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      |  3 ++
 target/mips/tcg/msa_translate.c | 91 +++++++++------------------------
 2 files changed, 28 insertions(+), 66 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index e97490cf880..88757f547eb 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -78,6 +78,9 @@ BNZ                 010001 111 .. ..... ................    @bz
   SRLRI             011110 011 ....... ..... .....  001010  @bit
 
   FILL              011110 11000000 .. ..... .....  011110  @2r
+  PCNT              011110 11000001 .. ..... .....  011110  @2r
+  NLOC              011110 11000010 .. ..... .....  011110  @2r
+  NLZC              011110 11000011 .. ..... .....  011110  @2r
   FCLASS            011110 110010000 . ..... .....  011110  @2rf
   FTRUNC_S          011110 110010001 . ..... .....  011110  @2rf
   FTRUNC_U          011110 110010010 . ..... .....  011110  @2rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index fc0b80f83ac..f54e9d173ac 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -50,13 +50,6 @@ enum {
     OPC_BMZ_V       = (0x05 << 21) | OPC_MSA_VEC,
     OPC_BSEL_V      = (0x06 << 21) | OPC_MSA_VEC,
 
-    OPC_MSA_2R      = (0x18 << 21) | OPC_MSA_VEC,
-
-    /* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
-    OPC_PCNT_df     = (0x01 << 18) | OPC_MSA_2R,
-    OPC_NLOC_df     = (0x02 << 18) | OPC_MSA_2R,
-    OPC_NLZC_df     = (0x03 << 18) | OPC_MSA_2R,
-
     /* 3R instruction df(bits 22..21) = _b, _h, _w, d */
     OPC_SLL_df      = (0x0 << 23) | OPC_MSA_3R_0D,
     OPC_ADDV_df     = (0x0 << 23) | OPC_MSA_3R_0E,
@@ -1832,75 +1825,44 @@ static void gen_msa_3rf(DisasContext *ctx)
     tcg_temp_free_i32(twt);
 }
 
-static void gen_msa_2r(DisasContext *ctx)
+static bool trans_msa_2r(DisasContext *ctx, arg_msa_r *a,
+                         void (*gen_msa_2r_b)(TCGv_ptr, TCGv_i32, TCGv_i32),
+                         void (*gen_msa_2r_h)(TCGv_ptr, TCGv_i32, TCGv_i32),
+                         void (*gen_msa_2r_w)(TCGv_ptr, TCGv_i32, TCGv_i32),
+                         void (*gen_msa_2r_d)(TCGv_ptr, TCGv_i32, TCGv_i32))
 {
-#define MASK_MSA_2R(op)     (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
-                            (op & (0x7 << 18)))
-    uint8_t ws = (ctx->opcode >> 11) & 0x1f;
-    uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-    uint8_t df = (ctx->opcode >> 16) & 0x3;
-    TCGv_i32 twd = tcg_const_i32(wd);
-    TCGv_i32 tws = tcg_const_i32(ws);
+    TCGv_i32 twd = tcg_const_i32(a->wd);
+    TCGv_i32 tws = tcg_const_i32(a->ws);
 
-    switch (MASK_MSA_2R(ctx->opcode)) {
-    case OPC_NLOC_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_nloc_b(cpu_env, twd, tws);
-            break;
-        case DF_HALF:
-            gen_helper_msa_nloc_h(cpu_env, twd, tws);
-            break;
-        case DF_WORD:
-            gen_helper_msa_nloc_w(cpu_env, twd, tws);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_nloc_d(cpu_env, twd, tws);
-            break;
+    switch (a->df) {
+    case DF_BYTE:
+        if (gen_msa_2r_b == NULL) {
+            gen_reserved_instruction(ctx);
+        } else {
+            gen_msa_2r_b(cpu_env, twd, tws);
         }
         break;
-    case OPC_NLZC_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_nlzc_b(cpu_env, twd, tws);
-            break;
-        case DF_HALF:
-            gen_helper_msa_nlzc_h(cpu_env, twd, tws);
-            break;
-        case DF_WORD:
-            gen_helper_msa_nlzc_w(cpu_env, twd, tws);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_nlzc_d(cpu_env, twd, tws);
-            break;
-        }
+    case DF_HALF:
+        gen_msa_2r_h(cpu_env, twd, tws);
         break;
-    case OPC_PCNT_df:
-        switch (df) {
-        case DF_BYTE:
-            gen_helper_msa_pcnt_b(cpu_env, twd, tws);
-            break;
-        case DF_HALF:
-            gen_helper_msa_pcnt_h(cpu_env, twd, tws);
-            break;
-        case DF_WORD:
-            gen_helper_msa_pcnt_w(cpu_env, twd, tws);
-            break;
-        case DF_DOUBLE:
-            gen_helper_msa_pcnt_d(cpu_env, twd, tws);
-            break;
-        }
+    case DF_WORD:
+        gen_msa_2r_w(cpu_env, twd, tws);
         break;
-    default:
-        MIPS_INVAL("MSA instruction");
-        gen_reserved_instruction(ctx);
+    case DF_DOUBLE:
+        gen_msa_2r_d(cpu_env, twd, tws);
         break;
     }
 
     tcg_temp_free_i32(twd);
     tcg_temp_free_i32(tws);
+
+    return true;
 }
 
+TRANS_DF_E(PCNT, trans_msa_2r, gen_helper_msa_pcnt);
+TRANS_DF_E(NLOC, trans_msa_2r, gen_helper_msa_nloc);
+TRANS_DF_E(NLZC, trans_msa_2r, gen_helper_msa_nlzc);
+
 static bool trans_FILL(DisasContext *ctx, arg_msa_r *a)
 {
     TCGv_i32 twd;
@@ -2018,9 +1980,6 @@ static void gen_msa_vec(DisasContext *ctx)
     case OPC_BSEL_V:
         gen_msa_vec_v(ctx);
         break;
-    case OPC_MSA_2R:
-        gen_msa_2r(ctx);
-        break;
     default:
         MIPS_INVAL("MSA instruction");
         gen_reserved_instruction(ctx);
-- 
2.31.1



  parent reply	other threads:[~2021-10-23 22:02 UTC|newest]

Thread overview: 78+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes " Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 01/33] tests/tcg: Fix some targets default cross compiler path Philippe Mathieu-Daudé
2021-10-23 23:24   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 02/33] target/mips: Fix MSA MADDV.B opcode Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 03/33] target/mips: Fix MSA MSUBV.B opcode Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 04/33] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation Philippe Mathieu-Daudé
2021-10-27 10:38   ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 05/33] target/mips: Have check_msa_access() return a boolean Philippe Mathieu-Daudé
2021-10-24  1:02   ` Richard Henderson
2021-10-24 12:48     ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 06/33] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum Philippe Mathieu-Daudé
2021-10-24  1:03   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 07/33] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v Philippe Mathieu-Daudé
2021-10-24  1:05   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 08/33] target/mips: Convert MSA LDI opcode to decodetree Philippe Mathieu-Daudé
2021-10-24  1:53   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 09/33] target/mips: Introduce generic TRANS_CHECK() for decodetree helpers Philippe Mathieu-Daudé
2021-10-24  1:58   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 10/33] target/mips: Extract df_extract() helper Philippe Mathieu-Daudé
2021-10-24  2:26   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 11/33] target/mips: Convert MSA I5 instruction format to decodetree Philippe Mathieu-Daudé
2021-10-24  2:10   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 12/33] target/mips: Convert MSA BIT " Philippe Mathieu-Daudé
2021-10-24  2:45   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 13/33] target/mips: Convert MSA SHF opcode " Philippe Mathieu-Daudé
2021-10-24  3:40   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 14/33] target/mips: Convert MSA I8 instruction format " Philippe Mathieu-Daudé
2021-10-24  3:45   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 15/33] target/mips: Convert MSA load/store " Philippe Mathieu-Daudé
2021-10-24  4:53   ` Richard Henderson
2021-10-24 11:18     ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 16/33] target/mips: Convert MSA 2RF " Philippe Mathieu-Daudé
2021-10-24  5:01   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 17/33] target/mips: Convert MSA FILL opcode " Philippe Mathieu-Daudé
2021-10-24  5:04   ` Richard Henderson
2021-10-24 16:44     ` Philippe Mathieu-Daudé
2021-10-24 17:26       ` Richard Henderson
2021-10-25 16:43         ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` Philippe Mathieu-Daudé [this message]
2021-10-24  5:14   ` [PATCH 18/33] target/mips: Convert MSA 2R instruction format " Richard Henderson
2021-10-23 21:47 ` [PATCH 19/33] target/mips: Convert MSA VEC " Philippe Mathieu-Daudé
2021-10-24  5:17   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 20/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Philippe Mathieu-Daudé
2021-10-24 17:37   ` Richard Henderson
2021-10-24 17:42     ` Richard Henderson
2021-10-23 21:47 ` [PATCH 21/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) Philippe Mathieu-Daudé
2021-10-24 17:42   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 22/33] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) Philippe Mathieu-Daudé
2021-10-24 17:51   ` Richard Henderson
2021-10-24 17:52   ` Richard Henderson
2021-10-24 18:57     ` Philippe Mathieu-Daudé
2021-10-24 20:27       ` Richard Henderson
2021-10-23 21:47 ` [PATCH 23/33] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Philippe Mathieu-Daudé
2021-10-24 17:55   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 24/33] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) Philippe Mathieu-Daudé
2021-10-24 18:09   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 25/33] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) Philippe Mathieu-Daudé
2021-10-24 18:12   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 26/33] target/mips: Convert MSA ELM instruction format to decodetree Philippe Mathieu-Daudé
2021-10-24 20:52   ` Richard Henderson
2021-10-27 17:27     ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 27/33] target/mips: Convert MSA COPY_U opcode " Philippe Mathieu-Daudé
2021-10-24 21:01   ` Richard Henderson
2021-10-27 17:40     ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 28/33] target/mips: Convert MSA COPY_S and INSERT opcodes " Philippe Mathieu-Daudé
2021-10-24 21:02   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 29/33] target/mips: Convert MSA MOVE.V opcode " Philippe Mathieu-Daudé
2021-10-24 21:09   ` Richard Henderson
2021-10-23 21:48 ` [PATCH 30/33] target/mips: Convert CFCMSA and CTCMSA opcodes " Philippe Mathieu-Daudé
2021-10-24 21:15   ` Richard Henderson
2021-10-23 21:48 ` [PATCH 31/33] target/mips: Remove generic MSA opcode Philippe Mathieu-Daudé
2021-10-24 21:16   ` Richard Henderson
2021-10-23 21:48 ` [PATCH 32/33] target/mips: Remove one MSA unnecessary decodetree overlap group Philippe Mathieu-Daudé
2021-10-24 21:17   ` Richard Henderson
2021-10-23 21:48 ` [PATCH 33/33] target/mips: Adjust style in msa_translate_init() Philippe Mathieu-Daudé
2021-10-24 21:18   ` Richard Henderson
2021-10-24 18:26 ` [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Jiaxun Yang
2021-10-24 19:01   ` Philippe Mathieu-Daudé

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