qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
	"Luis Pires" <luis.pires@eldorado.org.br>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PATCH 13/33] target/mips: Convert MSA SHF opcode to decodetree
Date: Sat, 23 Oct 2021 23:47:43 +0200	[thread overview]
Message-ID: <20211023214803.522078-14-f4bug@amsat.org> (raw)
In-Reply-To: <20211023214803.522078-1-f4bug@amsat.org>

Convert the SHF opcode (Immediate Set Shuffle Elements) to decodetree.

Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      |  3 +++
 target/mips/tcg/msa_translate.c | 47 +++++++++++++++++++++------------
 2 files changed, 33 insertions(+), 17 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 91d71ff560c..6347468a709 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -22,6 +22,7 @@
 @u5                 ...... ... df:2 sa:5  ws:5 wd:5 ......  &msa_ldst
 @s5                 ...... ... df:2 sa:s5 ws:5 wd:5 ......  &msa_ldst
 @ldi                ...... ... df:2 sa:s10     wd:5 ......  &msa_ldst ws=0
+@i8_df              ......     df:2 sa:s8 ws:5 wd:5 ......  &msa_ldst
 @bit                ...... ... df:7       ws:5 wd:5 ......  &msa_ldst sa=0
 
 LSA                 000000 ..... ..... ..... 000 .. 000101  @lsa
@@ -33,6 +34,8 @@ BZ                  010001 110 .. ..... ................    @bz
 BNZ                 010001 111 .. ..... ................    @bz
 
 {
+  SHF               011110 .. ........ ..... .....  000010  @i8_df
+
   ADDVI             011110 000 .. ..... ..... ..... 000110  @u5
   SUBVI             011110 001 .. ..... ..... ..... 000110  @u5
   MAXI_S            011110 010 .. ..... ..... ..... 000110  @s5
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 10bbe25172a..7cb078bfe92 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -57,13 +57,10 @@ enum {
     /* I8 instruction */
     OPC_ANDI_B      = (0x0 << 24) | OPC_MSA_I8_00,
     OPC_BMNZI_B     = (0x0 << 24) | OPC_MSA_I8_01,
-    OPC_SHF_B       = (0x0 << 24) | OPC_MSA_I8_02,
     OPC_ORI_B       = (0x1 << 24) | OPC_MSA_I8_00,
     OPC_BMZI_B      = (0x1 << 24) | OPC_MSA_I8_01,
-    OPC_SHF_H       = (0x1 << 24) | OPC_MSA_I8_02,
     OPC_NORI_B      = (0x2 << 24) | OPC_MSA_I8_00,
     OPC_BSELI_B     = (0x2 << 24) | OPC_MSA_I8_01,
-    OPC_SHF_W       = (0x2 << 24) | OPC_MSA_I8_02,
     OPC_XORI_B      = (0x3 << 24) | OPC_MSA_I8_00,
 
     /* VEC/2R/2RF instruction */
@@ -454,20 +451,6 @@ static void gen_msa_i8(DisasContext *ctx)
     case OPC_BSELI_B:
         gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8);
         break;
-    case OPC_SHF_B:
-    case OPC_SHF_H:
-    case OPC_SHF_W:
-        {
-            uint8_t df = (ctx->opcode >> 24) & 0x3;
-            if (df == DF_DOUBLE) {
-                gen_reserved_instruction(ctx);
-            } else {
-                TCGv_i32 tdf = tcg_const_i32(df);
-                gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8);
-                tcg_temp_free_i32(tdf);
-            }
-        }
-        break;
     default:
         MIPS_INVAL("MSA instruction");
         gen_reserved_instruction(ctx);
@@ -479,6 +462,36 @@ static void gen_msa_i8(DisasContext *ctx)
     tcg_temp_free_i32(ti8);
 }
 
+static bool trans_SHF(DisasContext *ctx, arg_msa_ldst *a)
+{
+    TCGv_i32 tdf;
+    TCGv_i32 twd;
+    TCGv_i32 tws;
+    TCGv_i32 timm;
+
+    if (a->df == DF_DOUBLE) {
+        gen_reserved_instruction(ctx);
+        return true;
+    }
+
+    if (!check_msa_access(ctx)) {
+        return false;
+    }
+
+    tdf = tcg_constant_i32(a->df);
+    twd = tcg_const_i32(a->wd);
+    tws = tcg_const_i32(a->ws);
+    timm = tcg_const_i32(a->sa);
+
+    gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, timm);
+
+    tcg_temp_free_i32(tws);
+    tcg_temp_free_i32(twd);
+    tcg_temp_free_i32(timm);
+
+    return true;
+}
+
 static bool trans_msa_i5(DisasContext *ctx, arg_msa_ldst *a,
                          void (*gen_msa_i5)(TCGv_ptr, TCGv_i32, TCGv_i32,
                                             TCGv_i32, TCGv_i32))
-- 
2.31.1



  parent reply	other threads:[~2021-10-23 21:59 UTC|newest]

Thread overview: 78+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-23 21:47 [PATCH 00/33] target/mips: Fully convert MSA opcodes " Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 01/33] tests/tcg: Fix some targets default cross compiler path Philippe Mathieu-Daudé
2021-10-23 23:24   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 02/33] target/mips: Fix MSA MADDV.B opcode Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 03/33] target/mips: Fix MSA MSUBV.B opcode Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 04/33] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation Philippe Mathieu-Daudé
2021-10-27 10:38   ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 05/33] target/mips: Have check_msa_access() return a boolean Philippe Mathieu-Daudé
2021-10-24  1:02   ` Richard Henderson
2021-10-24 12:48     ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 06/33] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum Philippe Mathieu-Daudé
2021-10-24  1:03   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 07/33] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v Philippe Mathieu-Daudé
2021-10-24  1:05   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 08/33] target/mips: Convert MSA LDI opcode to decodetree Philippe Mathieu-Daudé
2021-10-24  1:53   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 09/33] target/mips: Introduce generic TRANS_CHECK() for decodetree helpers Philippe Mathieu-Daudé
2021-10-24  1:58   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 10/33] target/mips: Extract df_extract() helper Philippe Mathieu-Daudé
2021-10-24  2:26   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 11/33] target/mips: Convert MSA I5 instruction format to decodetree Philippe Mathieu-Daudé
2021-10-24  2:10   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 12/33] target/mips: Convert MSA BIT " Philippe Mathieu-Daudé
2021-10-24  2:45   ` Richard Henderson
2021-10-23 21:47 ` Philippe Mathieu-Daudé [this message]
2021-10-24  3:40   ` [PATCH 13/33] target/mips: Convert MSA SHF opcode " Richard Henderson
2021-10-23 21:47 ` [PATCH 14/33] target/mips: Convert MSA I8 instruction format " Philippe Mathieu-Daudé
2021-10-24  3:45   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 15/33] target/mips: Convert MSA load/store " Philippe Mathieu-Daudé
2021-10-24  4:53   ` Richard Henderson
2021-10-24 11:18     ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 16/33] target/mips: Convert MSA 2RF " Philippe Mathieu-Daudé
2021-10-24  5:01   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 17/33] target/mips: Convert MSA FILL opcode " Philippe Mathieu-Daudé
2021-10-24  5:04   ` Richard Henderson
2021-10-24 16:44     ` Philippe Mathieu-Daudé
2021-10-24 17:26       ` Richard Henderson
2021-10-25 16:43         ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 18/33] target/mips: Convert MSA 2R instruction format " Philippe Mathieu-Daudé
2021-10-24  5:14   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 19/33] target/mips: Convert MSA VEC " Philippe Mathieu-Daudé
2021-10-24  5:17   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 20/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Philippe Mathieu-Daudé
2021-10-24 17:37   ` Richard Henderson
2021-10-24 17:42     ` Richard Henderson
2021-10-23 21:47 ` [PATCH 21/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) Philippe Mathieu-Daudé
2021-10-24 17:42   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 22/33] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) Philippe Mathieu-Daudé
2021-10-24 17:51   ` Richard Henderson
2021-10-24 17:52   ` Richard Henderson
2021-10-24 18:57     ` Philippe Mathieu-Daudé
2021-10-24 20:27       ` Richard Henderson
2021-10-23 21:47 ` [PATCH 23/33] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Philippe Mathieu-Daudé
2021-10-24 17:55   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 24/33] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) Philippe Mathieu-Daudé
2021-10-24 18:09   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 25/33] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) Philippe Mathieu-Daudé
2021-10-24 18:12   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 26/33] target/mips: Convert MSA ELM instruction format to decodetree Philippe Mathieu-Daudé
2021-10-24 20:52   ` Richard Henderson
2021-10-27 17:27     ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 27/33] target/mips: Convert MSA COPY_U opcode " Philippe Mathieu-Daudé
2021-10-24 21:01   ` Richard Henderson
2021-10-27 17:40     ` Philippe Mathieu-Daudé
2021-10-23 21:47 ` [PATCH 28/33] target/mips: Convert MSA COPY_S and INSERT opcodes " Philippe Mathieu-Daudé
2021-10-24 21:02   ` Richard Henderson
2021-10-23 21:47 ` [PATCH 29/33] target/mips: Convert MSA MOVE.V opcode " Philippe Mathieu-Daudé
2021-10-24 21:09   ` Richard Henderson
2021-10-23 21:48 ` [PATCH 30/33] target/mips: Convert CFCMSA and CTCMSA opcodes " Philippe Mathieu-Daudé
2021-10-24 21:15   ` Richard Henderson
2021-10-23 21:48 ` [PATCH 31/33] target/mips: Remove generic MSA opcode Philippe Mathieu-Daudé
2021-10-24 21:16   ` Richard Henderson
2021-10-23 21:48 ` [PATCH 32/33] target/mips: Remove one MSA unnecessary decodetree overlap group Philippe Mathieu-Daudé
2021-10-24 21:17   ` Richard Henderson
2021-10-23 21:48 ` [PATCH 33/33] target/mips: Adjust style in msa_translate_init() Philippe Mathieu-Daudé
2021-10-24 21:18   ` Richard Henderson
2021-10-24 18:26 ` [PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree Jiaxun Yang
2021-10-24 19:01   ` Philippe Mathieu-Daudé

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20211023214803.522078-14-f4bug@amsat.org \
    --to=f4bug@amsat.org \
    --cc=aleksandar.rikalo@syrmia.com \
    --cc=luis.pires@eldorado.org.br \
    --cc=qemu-devel@nongnu.org \
    --cc=richard.henderson@linaro.org \
    --subject='Re: [PATCH 13/33] target/mips: Convert MSA SHF opcode to decodetree' \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).