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From: matheus.ferst@eldorado.org.br
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: lucas.castro@eldorado.org.br, richard.henderson@linaro.org,
	groug@kaod.org, luis.pires@eldorado.org.br,
	matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au
Subject: [PATCH 05/33] target/ppc: Move LQ and STQ to decodetree
Date: Thu, 21 Oct 2021 16:45:19 -0300	[thread overview]
Message-ID: <20211021194547.672988-6-matheus.ferst@eldorado.org.br> (raw)
In-Reply-To: <20211021194547.672988-1-matheus.ferst@eldorado.org.br>

From: Matheus Ferst <matheus.ferst@eldorado.org.br>

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
 target/ppc/insn32.decode                   |  11 ++
 target/ppc/translate.c                     | 156 +--------------------
 target/ppc/translate/fixedpoint-impl.c.inc |  98 +++++++++++++
 3 files changed, 114 insertions(+), 151 deletions(-)

diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 3837b799c8..9cb9fc00b8 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -24,9 +24,16 @@
 @D_bfs          ...... bf:3 - l:1 ra:5 imm:s16          &D_bf
 @D_bfu          ...... bf:3 - l:1 ra:5 imm:16           &D_bf
 
+%dq_si          4:s12  !function=times_16
+%dq_rtp         22:4   !function=times_2
+@DQ_rtp         ...... ....0 ra:5 ............ ....             &D rt=%dq_rtp si=%dq_si
+
 %ds_si          2:s14  !function=times_4
 @DS             ...... rt:5 ra:5 .............. ..      &D si=%ds_si
 
+%ds_rtp         22:4   !function=times_2
+@DS_rtp         ...... ....0 ra:5 .............. ..             &D rt=%ds_rtp si=%ds_si
+
 &DX             rt d
 %dx_d           6:s10 16:5 0:1
 @DX             ...... rt:5  ..... .......... ..... .   &DX d=%dx_d
@@ -153,6 +160,8 @@ LDU             111010 ..... ..... ..............01     @DS
 LDX             011111 ..... ..... ..... 0000010101 -   @X
 LDUX            011111 ..... ..... ..... 0000110101 -   @X
 
+LQ              111000 ..... ..... ............ ----    @DQ_rtp
+
 ### Fixed-Point Store Instructions
 
 STB             100110 ..... ..... ................     @D
@@ -175,6 +184,8 @@ STDU            111110 ..... ..... ..............01     @DS
 STDX            011111 ..... ..... ..... 0010010101 -   @X
 STDUX           011111 ..... ..... ..... 0010110101 -   @X
 
+STQ             111110 ..... ..... ..............10     @DS_rtp
+
 ### Fixed-Point Compare Instructions
 
 CMP             011111 ... - . ..... ..... 0000000000 - @X_bfl
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 39f03ac658..738101088e 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3325,69 +3325,6 @@ GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
-
-/* lq */
-static void gen_lq(DisasContext *ctx)
-{
-    int ra, rd;
-    TCGv EA, hi, lo;
-
-    /* lq is a legal user mode instruction starting in ISA 2.07 */
-    bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
-    bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
-
-    if (!legal_in_user_mode && ctx->pr) {
-        gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
-        return;
-    }
-
-    if (!le_is_supported && ctx->le_mode) {
-        gen_align_no_le(ctx);
-        return;
-    }
-    ra = rA(ctx->opcode);
-    rd = rD(ctx->opcode);
-    if (unlikely((rd & 1) || rd == ra)) {
-        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
-        return;
-    }
-
-    gen_set_access_type(ctx, ACCESS_INT);
-    EA = tcg_temp_new();
-    gen_addr_imm_index(ctx, EA, 0x0F);
-
-    /* Note that the low part is always in RD+1, even in LE mode.  */
-    lo = cpu_gpr[rd + 1];
-    hi = cpu_gpr[rd];
-
-    if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
-        if (HAVE_ATOMIC128) {
-            TCGv_i32 oi = tcg_temp_new_i32();
-            if (ctx->le_mode) {
-                tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
-                gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
-            } else {
-                tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
-                gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
-            }
-            tcg_temp_free_i32(oi);
-            tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
-        } else {
-            /* Restart with exclusive lock.  */
-            gen_helper_exit_atomic(cpu_env);
-            ctx->base.is_jmp = DISAS_NORETURN;
-        }
-    } else if (ctx->le_mode) {
-        tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ);
-        gen_addr_add(ctx, EA, EA, 8);
-        tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ);
-    } else {
-        tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ);
-        gen_addr_add(ctx, EA, EA, 8);
-        tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ);
-    }
-    tcg_temp_free(EA);
-}
 #endif
 
 /***                              Integer store                            ***/
@@ -3433,90 +3370,6 @@ GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
-
-static void gen_std(DisasContext *ctx)
-{
-    int rs;
-    TCGv EA;
-
-    rs = rS(ctx->opcode);
-    if ((ctx->opcode & 0x3) == 0x2) { /* stq */
-        bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
-        bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
-        TCGv hi, lo;
-
-        if (!(ctx->insns_flags & PPC_64BX)) {
-            gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
-        }
-
-        if (!legal_in_user_mode && ctx->pr) {
-            gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
-            return;
-        }
-
-        if (!le_is_supported && ctx->le_mode) {
-            gen_align_no_le(ctx);
-            return;
-        }
-
-        if (unlikely(rs & 1)) {
-            gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
-            return;
-        }
-        gen_set_access_type(ctx, ACCESS_INT);
-        EA = tcg_temp_new();
-        gen_addr_imm_index(ctx, EA, 0x03);
-
-        /* Note that the low part is always in RS+1, even in LE mode.  */
-        lo = cpu_gpr[rs + 1];
-        hi = cpu_gpr[rs];
-
-        if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
-            if (HAVE_ATOMIC128) {
-                TCGv_i32 oi = tcg_temp_new_i32();
-                if (ctx->le_mode) {
-                    tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128,
-                                                        ctx->mem_idx));
-                    gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi);
-                } else {
-                    tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128,
-                                                        ctx->mem_idx));
-                    gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi);
-                }
-                tcg_temp_free_i32(oi);
-            } else {
-                /* Restart with exclusive lock.  */
-                gen_helper_exit_atomic(cpu_env);
-                ctx->base.is_jmp = DISAS_NORETURN;
-            }
-        } else if (ctx->le_mode) {
-            tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ);
-            gen_addr_add(ctx, EA, EA, 8);
-            tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ);
-        } else {
-            tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ);
-            gen_addr_add(ctx, EA, EA, 8);
-            tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ);
-        }
-        tcg_temp_free(EA);
-    } else {
-        /* std / stdu */
-        if (Rc(ctx->opcode)) {
-            if (unlikely(rA(ctx->opcode) == 0)) {
-                gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
-                return;
-            }
-        }
-        gen_set_access_type(ctx, ACCESS_INT);
-        EA = tcg_temp_new();
-        gen_addr_imm_index(ctx, EA, 0x03);
-        gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
-        if (Rc(ctx->opcode)) {
-            tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
-        }
-        tcg_temp_free(EA);
-    }
-}
 #endif
 /***                Integer load and store with byte reverse               ***/
 
@@ -7460,6 +7313,11 @@ static int times_4(DisasContext *ctx, int x)
     return x * 4;
 }
 
+static int times_16(DisasContext *ctx, int x)
+{
+    return x * 16;
+}
+
 /*
  * Helpers for trans_* functions to check for specific insns flags.
  * Use token pasting to ensure that we use the proper flag with the
@@ -7715,10 +7573,6 @@ GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
                PPC_NONE, PPC2_ISA300),
 #endif
-#if defined(TARGET_PPC64)
-GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
-GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
-#endif
 /* handles lfdp, lxsd, lxssp */
 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
 /* handles stfdp, lxv, stxsd, stxssp, stxv */
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 1c35b60eb4..61d129fb5d 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -70,6 +70,98 @@ static bool do_ldst_X(DisasContext *ctx, arg_X *a, bool update,
     return do_ldst(ctx, a->rt, a->ra, cpu_gpr[a->rb], update, store, mop);
 }
 
+static bool do_ldst_quad(DisasContext *ctx, arg_D *a, bool store, bool prefixed)
+{
+#if defined(TARGET_PPC64)
+    TCGv ea;
+    TCGv_i64 low_addr_gpr, high_addr_gpr;
+    MemOp mop;
+
+    REQUIRE_INSNS_FLAGS(ctx, 64BX);
+
+    if (!prefixed && !(ctx->insns_flags2 & PPC2_LSQ_ISA207)) {
+        if (ctx->pr) {
+            /* lq and stq were privileged prior to V. 2.07 */
+            gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
+            return true;
+        }
+
+        if (ctx->le_mode) {
+            gen_align_no_le(ctx);
+            return true;
+        }
+    }
+
+    if (!store && unlikely(a->ra == a->rt)) {
+        gen_invalid(ctx);
+        return true;
+    }
+
+    gen_set_access_type(ctx, ACCESS_INT);
+    ea = tcg_temp_new();
+    do_ea_calc(ctx, a->ra, tcg_constant_tl(a->si), ea);
+
+    if (prefixed || !ctx->le_mode) {
+        low_addr_gpr = cpu_gpr[a->rt];
+        high_addr_gpr = cpu_gpr[a->rt + 1];
+    } else {
+        low_addr_gpr = cpu_gpr[a->rt + 1];
+        high_addr_gpr = cpu_gpr[a->rt];
+    }
+
+    if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
+        if (HAVE_ATOMIC128) {
+            mop = DEF_MEMOP(MO_128);
+            TCGv_i32 oi = tcg_constant_i32(make_memop_idx(mop, ctx->mem_idx));
+            if (store) {
+                if (ctx->le_mode) {
+                    gen_helper_stq_le_parallel(cpu_env, ea, low_addr_gpr,
+                                               high_addr_gpr, oi);
+                } else {
+                    gen_helper_stq_be_parallel(cpu_env, ea, high_addr_gpr,
+                                               low_addr_gpr, oi);
+
+                }
+            } else {
+                if (ctx->le_mode) {
+                    gen_helper_lq_le_parallel(low_addr_gpr, cpu_env, ea, oi);
+                    tcg_gen_ld_i64(high_addr_gpr, cpu_env,
+                                   offsetof(CPUPPCState, retxh));
+                } else {
+                    gen_helper_lq_be_parallel(high_addr_gpr, cpu_env, ea, oi);
+                    tcg_gen_ld_i64(low_addr_gpr, cpu_env,
+                                   offsetof(CPUPPCState, retxh));
+                }
+            }
+        } else {
+            /* Restart with exclusive lock.  */
+            gen_helper_exit_atomic(cpu_env);
+            ctx->base.is_jmp = DISAS_NORETURN;
+        }
+    } else {
+        mop = DEF_MEMOP(MO_Q);
+        if (store) {
+            tcg_gen_qemu_st_i64(low_addr_gpr, ea, ctx->mem_idx, mop);
+        } else {
+            tcg_gen_qemu_ld_i64(low_addr_gpr, ea, ctx->mem_idx, mop);
+        }
+
+        gen_addr_add(ctx, ea, ea, 8);
+
+        if (store) {
+            tcg_gen_qemu_st_i64(high_addr_gpr, ea, ctx->mem_idx, mop);
+        } else {
+            tcg_gen_qemu_ld_i64(high_addr_gpr, ea, ctx->mem_idx, mop);
+        }
+    }
+    tcg_temp_free(ea);
+#else
+    qemu_build_not_reached();
+#endif
+
+    return true;
+}
+
 /* Load Byte and Zero */
 TRANS(LBZ, do_ldst_D, false, false, MO_UB)
 TRANS(LBZX, do_ldst_X, false, false, MO_UB)
@@ -111,6 +203,9 @@ TRANS64(LDU, do_ldst_D, true, false, MO_Q)
 TRANS64(LDUX, do_ldst_X, true, false, MO_Q)
 TRANS64(PLD, do_ldst_PLS_D, false, false, MO_Q)
 
+/* Load Quadword */
+TRANS64(LQ, do_ldst_quad, false, false);
+
 /* Store Byte */
 TRANS(STB, do_ldst_D, false, true, MO_UB)
 TRANS(STBX, do_ldst_X, false, true, MO_UB)
@@ -139,6 +234,9 @@ TRANS64(STDU, do_ldst_D, true, true, MO_Q)
 TRANS64(STDUX, do_ldst_X, true, true, MO_Q)
 TRANS64(PSTD, do_ldst_PLS_D, false, true, MO_Q)
 
+/* Store Quadword */
+TRANS64(STQ, do_ldst_quad, true, false);
+
 /*
  * Fixed-Point Compare Instructions
  */
-- 
2.25.1



  parent reply	other threads:[~2021-10-21 19:55 UTC|newest]

Thread overview: 84+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-21 19:45 [PATCH 00/33] PowerISA v3.1 instruction batch matheus.ferst
2021-10-21 19:45 ` [PATCH 01/33] target/ppc: introduce do_ea_calc matheus.ferst
2021-10-22 21:51   ` Richard Henderson
2021-10-22 21:57   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 02/33] target/ppc: move resolve_PLS_D to translate.c matheus.ferst
2021-10-22 22:01   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 03/33] target/ppc: Move load and store floating point instructions to decodetree matheus.ferst
2021-10-22 22:19   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 04/33] target/ppc: Implement PLFS, PLFD, PSTFS and PSTFD instructions matheus.ferst
2021-10-22 22:24   ` Richard Henderson
2021-10-21 19:45 ` matheus.ferst [this message]
2021-10-22 22:53   ` [PATCH 05/33] target/ppc: Move LQ and STQ to decodetree Richard Henderson
2021-10-21 19:45 ` [PATCH 06/33] target/ppc: Implement PLQ and PSTQ matheus.ferst
2021-10-22 22:54   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 07/33] target/ppc: Implement cntlzdm matheus.ferst
2021-10-22 23:16   ` Richard Henderson
2021-10-26 14:33     ` Matheus K. Ferst
2021-10-21 19:45 ` [PATCH 08/33] target/ppc: Implement cnttzdm matheus.ferst
2021-10-22 23:55   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 09/33] target/ppc: Implement pdepd instruction matheus.ferst
2021-10-23  0:04   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 10/33] target/ppc: Implement pextd instruction matheus.ferst
2021-10-23  0:26   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 11/33] target/ppc: Move vcfuged to vmx-impl.c.inc matheus.ferst
2021-10-23  0:31   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 12/33] target/ppc: Implement vclzdm/vctzdm instructions matheus.ferst
2021-10-23  0:34   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 13/33] target/ppc: Implement vpdepd/vpextd instruction matheus.ferst
2021-10-23  0:38   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 14/33] target/ppc: Implement vsldbi/vsrdbi instructions matheus.ferst
2021-10-23  4:07   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 15/33] target/ppc: Implement Vector Insert from GPR using GPR index insns matheus.ferst
2021-10-23  4:37   ` Richard Henderson
2021-10-23  4:40   ` Richard Henderson
2021-10-23 10:12     ` BALATON Zoltan
2021-10-23 18:36       ` Richard Henderson
2021-10-23 20:02         ` BALATON Zoltan
2021-10-23 20:09           ` Richard Henderson
2021-10-26 14:33     ` Matheus K. Ferst
2021-10-21 19:45 ` [PATCH 16/33] target/ppc: Implement Vector Insert Word from GPR using Immediate insns matheus.ferst
2021-10-23  4:42   ` Richard Henderson
2021-10-26 14:33     ` Matheus K. Ferst
2021-10-26 16:58       ` Richard Henderson
2021-10-26 18:45         ` Paul A. Clarke
2021-10-27 11:49           ` Matheus K. Ferst
2021-10-21 19:45 ` [PATCH 17/33] target/ppc: Implement Vector Insert from VSR using GPR index insns matheus.ferst
2021-10-23  4:48   ` Richard Henderson
2021-10-23  4:54   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 18/33] target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree matheus.ferst
2021-10-23  4:53   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 19/33] target/ppc: Implement Vector Extract Double to VSR using GPR index insns matheus.ferst
2021-10-23 20:01   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 20/33] target/ppc: Introduce REQUIRE_VSX macro matheus.ferst
2021-10-23 20:10   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 21/33] target/ppc: moved stxv and lxv from legacy to decodtree matheus.ferst
2021-10-23 20:34   ` Richard Henderson
2021-10-23 20:39     ` Richard Henderson
2021-10-23 20:46   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 22/33] target/ppc: moved stxvx and lxvx " matheus.ferst
2021-10-23 20:38   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 23/33] target/ppc: added the instructions LXVP and STXVP matheus.ferst
2021-10-23 20:48   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 24/33] target/ppc: added the instructions LXVPX and STXVPX matheus.ferst
2021-10-23 20:49   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 25/33] target/ppc: added the instructions PLXV and PSTXV matheus.ferst
2021-10-23 20:56   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 26/33] target/ppc: added the instructions PLXVP and PSTXVP matheus.ferst
2021-10-23 20:57   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 27/33] target/ppc: moved XXSPLTW to using decodetree matheus.ferst
2021-10-23 21:03   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 28/33] target/ppc: moved XXSPLTIB " matheus.ferst
2021-10-23 21:06   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 29/33] target/ppc: implemented XXSPLTI32DX matheus.ferst
2021-10-23 21:12   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 30/33] target/ppc: Implemented XXSPLTIW using decodetree matheus.ferst
2021-10-23 21:15   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 31/33] target/ppc: implemented XXSPLTIDP instruction matheus.ferst
2021-10-23 21:19   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 32/33] target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions matheus.ferst
2021-10-23 21:24   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 33/33] target/ppc: Implement lxvkq instruction matheus.ferst
2021-10-23 21:29   ` Richard Henderson
2021-10-22  2:06 ` [PATCH 00/33] PowerISA v3.1 instruction batch Richard Henderson
2021-10-22 11:13   ` Matheus K. Ferst

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    --to=matheus.ferst@eldorado.org.br \
    --cc=david@gibson.dropbear.id.au \
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    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    --cc=richard.henderson@linaro.org \
    --subject='Re: [PATCH 05/33] target/ppc: Move LQ and STQ to decodetree' \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

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