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From: matheus.ferst@eldorado.org.br
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: lucas.castro@eldorado.org.br, richard.henderson@linaro.org,
	groug@kaod.org, luis.pires@eldorado.org.br,
	matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au
Subject: [PATCH 18/33] target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree
Date: Thu, 21 Oct 2021 16:45:32 -0300	[thread overview]
Message-ID: <20211021194547.672988-19-matheus.ferst@eldorado.org.br> (raw)
In-Reply-To: <20211021194547.672988-1-matheus.ferst@eldorado.org.br>

From: Matheus Ferst <matheus.ferst@eldorado.org.br>

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
 target/ppc/helper.h                 |  4 ----
 target/ppc/insn32.decode            |  5 +++++
 target/ppc/int_helper.c             | 21 -------------------
 target/ppc/translate/vmx-impl.c.inc | 32 ++++++++++++++++++++---------
 target/ppc/translate/vmx-ops.c.inc  | 10 +++------
 5 files changed, 30 insertions(+), 42 deletions(-)

diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 45c74b540f..53c65ca1c7 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -226,10 +226,6 @@ DEF_HELPER_3(vextractub, void, avr, avr, i32)
 DEF_HELPER_3(vextractuh, void, avr, avr, i32)
 DEF_HELPER_3(vextractuw, void, avr, avr, i32)
 DEF_HELPER_3(vextractd, void, avr, avr, i32)
-DEF_HELPER_3(vinsertb, void, avr, avr, i32)
-DEF_HELPER_3(vinserth, void, avr, avr, i32)
-DEF_HELPER_3(vinsertw, void, avr, avr, i32)
-DEF_HELPER_3(vinsertd, void, avr, avr, i32)
 DEF_HELPER_4(VINSBLX, void, env, avr, i64, tl)
 DEF_HELPER_4(VINSHLX, void, env, avr, i64, tl)
 DEF_HELPER_4(VINSWLX, void, env, avr, i64, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index de410abf7d..2eb7fb4e92 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -347,6 +347,11 @@ VPEXTD          000100 ..... ..... ..... 10110001101    @VX
 
 ## Vector Permute and Formatting Instruction
 
+VINSERTB        000100 ..... - .... ..... 01100001101   @VX_uim4
+VINSERTH        000100 ..... - .... ..... 01101001101   @VX_uim4
+VINSERTW        000100 ..... - .... ..... 01110001101   @VX_uim4
+VINSERTD        000100 ..... - .... ..... 01111001101   @VX_uim4
+
 VINSBLX         000100 ..... ..... ..... 01000001111    @VX
 VINSBRX         000100 ..... ..... ..... 01100001111    @VX
 VINSHLX         000100 ..... ..... ..... 01001001111    @VX
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 0506358ad8..5a925a564d 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1646,27 +1646,6 @@ void helper_vslo(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
 #endif
 }
 
-#if defined(HOST_WORDS_BIGENDIAN)
-#define VINSERT(suffix, element)                                            \
-    void helper_vinsert##suffix(ppc_avr_t *r, ppc_avr_t *b, uint32_t index) \
-    {                                                                       \
-        memmove(&r->u8[index], &b->u8[8 - sizeof(r->element[0])],           \
-               sizeof(r->element[0]));                                      \
-    }
-#else
-#define VINSERT(suffix, element)                                            \
-    void helper_vinsert##suffix(ppc_avr_t *r, ppc_avr_t *b, uint32_t index) \
-    {                                                                       \
-        uint32_t d = (16 - index) - sizeof(r->element[0]);                  \
-        memmove(&r->u8[d], &b->u8[8], sizeof(r->element[0]));               \
-    }
-#endif
-VINSERT(b, u8)
-VINSERT(h, u16)
-VINSERT(w, u32)
-VINSERT(d, u64)
-#undef VINSERT
-
 #if defined(HOST_WORDS_BIGENDIAN)
 #define ELEM_ADDR(VEC, IDX, SIZE) (&(VEC)->VsrB(IDX))
 #else
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 03327d3fe4..7f98875192 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1217,10 +1217,6 @@ GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15);
 GEN_VXFORM_UIMM_SPLAT(vextractuh, 6, 9, 14);
 GEN_VXFORM_UIMM_SPLAT(vextractuw, 6, 10, 12);
 GEN_VXFORM_UIMM_SPLAT(vextractd, 6, 11, 8);
-GEN_VXFORM_UIMM_SPLAT(vinsertb, 6, 12, 15);
-GEN_VXFORM_UIMM_SPLAT(vinserth, 6, 13, 14);
-GEN_VXFORM_UIMM_SPLAT(vinsertw, 6, 14, 12);
-GEN_VXFORM_UIMM_SPLAT(vinsertd, 6, 15, 8);
 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
@@ -1231,12 +1227,6 @@ GEN_VXFORM_DUAL(vsplth, PPC_ALTIVEC, PPC_NONE,
                 vextractuh, PPC_NONE, PPC2_ISA300);
 GEN_VXFORM_DUAL(vspltw, PPC_ALTIVEC, PPC_NONE,
                 vextractuw, PPC_NONE, PPC2_ISA300);
-GEN_VXFORM_DUAL(vspltisb, PPC_ALTIVEC, PPC_NONE,
-                vinsertb, PPC_NONE, PPC2_ISA300);
-GEN_VXFORM_DUAL(vspltish, PPC_ALTIVEC, PPC_NONE,
-                vinserth, PPC_NONE, PPC2_ISA300);
-GEN_VXFORM_DUAL(vspltisw, PPC_ALTIVEC, PPC_NONE,
-                vinsertw, PPC_NONE, PPC2_ISA300);
 
 static bool do_vinsx(DisasContext *ctx, int vrt, int size, bool right, TCGv ra,
             TCGv_i64 rb, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
@@ -1338,6 +1328,23 @@ static bool do_vins_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size,
 #endif
 }
 
+static bool do_vinsert_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size,
+                        void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
+{
+    REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+    REQUIRE_VECTOR(ctx);
+
+    if (a->uim > (16 - size)) {
+        qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for VINSERT* at"
+            " 0x" TARGET_FMT_lx ", UIM = %d > %d\n", ctx->cia, a->uim,
+            16 - size);
+        return true;
+    }
+
+    return do_vinsvx(ctx, a->vrt, size, false, tcg_constant_tl(a->uim), a->vrb,
+                     gen_helper);
+}
+
 TRANS(VINSBLX, do_vinsx_VX, 1, false, gen_helper_VINSBLX)
 TRANS(VINSHLX, do_vinsx_VX, 2, false, gen_helper_VINSHLX)
 TRANS(VINSWLX, do_vinsx_VX, 4, false, gen_helper_VINSWLX)
@@ -1359,6 +1366,11 @@ TRANS(VINSBVRX, do_vinsvx_VX, 1, true, gen_helper_VINSBLX)
 TRANS(VINSHVRX, do_vinsvx_VX, 2, true, gen_helper_VINSHLX)
 TRANS(VINSWVRX, do_vinsvx_VX, 4, true, gen_helper_VINSWLX)
 
+TRANS(VINSERTB, do_vinsert_VX_uim4, 1, gen_helper_VINSBLX)
+TRANS(VINSERTH, do_vinsert_VX_uim4, 2, gen_helper_VINSHLX)
+TRANS(VINSERTW, do_vinsert_VX_uim4, 4, gen_helper_VINSWLX)
+TRANS(VINSERTD, do_vinsert_VX_uim4, 8, gen_helper_VINSDLX)
+
 static void gen_vsldoi(DisasContext *ctx)
 {
     TCGv_ptr ra, rb, rd;
diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc
index f3f4855111..25ee715b43 100644
--- a/target/ppc/translate/vmx-ops.c.inc
+++ b/target/ppc/translate/vmx-ops.c.inc
@@ -225,13 +225,9 @@ GEN_VXFORM_DUAL_INV(vsplth, vextractuh, 6, 9, 0x00000000, 0x100000,
 GEN_VXFORM_DUAL_INV(vspltw, vextractuw, 6, 10, 0x00000000, 0x100000,
                                                PPC_ALTIVEC),
 GEN_VXFORM_300_EXT(vextractd, 6, 11, 0x100000),
-GEN_VXFORM_DUAL_INV(vspltisb, vinsertb, 6, 12, 0x00000000, 0x100000,
-                                               PPC_ALTIVEC),
-GEN_VXFORM_DUAL_INV(vspltish, vinserth, 6, 13, 0x00000000, 0x100000,
-                                               PPC_ALTIVEC),
-GEN_VXFORM_DUAL_INV(vspltisw, vinsertw, 6, 14, 0x00000000, 0x100000,
-                                               PPC_ALTIVEC),
-GEN_VXFORM_300_EXT(vinsertd, 6, 15, 0x100000),
+GEN_VXFORM(vspltisb, 6, 12),
+GEN_VXFORM(vspltish, 6, 13),
+GEN_VXFORM(vspltisw, 6, 14),
 GEN_VXFORM_300_EO(vnegw, 0x01, 0x18, 0x06),
 GEN_VXFORM_300_EO(vnegd, 0x01, 0x18, 0x07),
 GEN_VXFORM_300_EO(vextsb2w, 0x01, 0x18, 0x10),
-- 
2.25.1



  parent reply	other threads:[~2021-10-21 20:39 UTC|newest]

Thread overview: 84+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-21 19:45 [PATCH 00/33] PowerISA v3.1 instruction batch matheus.ferst
2021-10-21 19:45 ` [PATCH 01/33] target/ppc: introduce do_ea_calc matheus.ferst
2021-10-22 21:51   ` Richard Henderson
2021-10-22 21:57   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 02/33] target/ppc: move resolve_PLS_D to translate.c matheus.ferst
2021-10-22 22:01   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 03/33] target/ppc: Move load and store floating point instructions to decodetree matheus.ferst
2021-10-22 22:19   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 04/33] target/ppc: Implement PLFS, PLFD, PSTFS and PSTFD instructions matheus.ferst
2021-10-22 22:24   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 05/33] target/ppc: Move LQ and STQ to decodetree matheus.ferst
2021-10-22 22:53   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 06/33] target/ppc: Implement PLQ and PSTQ matheus.ferst
2021-10-22 22:54   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 07/33] target/ppc: Implement cntlzdm matheus.ferst
2021-10-22 23:16   ` Richard Henderson
2021-10-26 14:33     ` Matheus K. Ferst
2021-10-21 19:45 ` [PATCH 08/33] target/ppc: Implement cnttzdm matheus.ferst
2021-10-22 23:55   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 09/33] target/ppc: Implement pdepd instruction matheus.ferst
2021-10-23  0:04   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 10/33] target/ppc: Implement pextd instruction matheus.ferst
2021-10-23  0:26   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 11/33] target/ppc: Move vcfuged to vmx-impl.c.inc matheus.ferst
2021-10-23  0:31   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 12/33] target/ppc: Implement vclzdm/vctzdm instructions matheus.ferst
2021-10-23  0:34   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 13/33] target/ppc: Implement vpdepd/vpextd instruction matheus.ferst
2021-10-23  0:38   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 14/33] target/ppc: Implement vsldbi/vsrdbi instructions matheus.ferst
2021-10-23  4:07   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 15/33] target/ppc: Implement Vector Insert from GPR using GPR index insns matheus.ferst
2021-10-23  4:37   ` Richard Henderson
2021-10-23  4:40   ` Richard Henderson
2021-10-23 10:12     ` BALATON Zoltan
2021-10-23 18:36       ` Richard Henderson
2021-10-23 20:02         ` BALATON Zoltan
2021-10-23 20:09           ` Richard Henderson
2021-10-26 14:33     ` Matheus K. Ferst
2021-10-21 19:45 ` [PATCH 16/33] target/ppc: Implement Vector Insert Word from GPR using Immediate insns matheus.ferst
2021-10-23  4:42   ` Richard Henderson
2021-10-26 14:33     ` Matheus K. Ferst
2021-10-26 16:58       ` Richard Henderson
2021-10-26 18:45         ` Paul A. Clarke
2021-10-27 11:49           ` Matheus K. Ferst
2021-10-21 19:45 ` [PATCH 17/33] target/ppc: Implement Vector Insert from VSR using GPR index insns matheus.ferst
2021-10-23  4:48   ` Richard Henderson
2021-10-23  4:54   ` Richard Henderson
2021-10-21 19:45 ` matheus.ferst [this message]
2021-10-23  4:53   ` [PATCH 18/33] target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree Richard Henderson
2021-10-21 19:45 ` [PATCH 19/33] target/ppc: Implement Vector Extract Double to VSR using GPR index insns matheus.ferst
2021-10-23 20:01   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 20/33] target/ppc: Introduce REQUIRE_VSX macro matheus.ferst
2021-10-23 20:10   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 21/33] target/ppc: moved stxv and lxv from legacy to decodtree matheus.ferst
2021-10-23 20:34   ` Richard Henderson
2021-10-23 20:39     ` Richard Henderson
2021-10-23 20:46   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 22/33] target/ppc: moved stxvx and lxvx " matheus.ferst
2021-10-23 20:38   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 23/33] target/ppc: added the instructions LXVP and STXVP matheus.ferst
2021-10-23 20:48   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 24/33] target/ppc: added the instructions LXVPX and STXVPX matheus.ferst
2021-10-23 20:49   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 25/33] target/ppc: added the instructions PLXV and PSTXV matheus.ferst
2021-10-23 20:56   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 26/33] target/ppc: added the instructions PLXVP and PSTXVP matheus.ferst
2021-10-23 20:57   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 27/33] target/ppc: moved XXSPLTW to using decodetree matheus.ferst
2021-10-23 21:03   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 28/33] target/ppc: moved XXSPLTIB " matheus.ferst
2021-10-23 21:06   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 29/33] target/ppc: implemented XXSPLTI32DX matheus.ferst
2021-10-23 21:12   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 30/33] target/ppc: Implemented XXSPLTIW using decodetree matheus.ferst
2021-10-23 21:15   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 31/33] target/ppc: implemented XXSPLTIDP instruction matheus.ferst
2021-10-23 21:19   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 32/33] target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions matheus.ferst
2021-10-23 21:24   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 33/33] target/ppc: Implement lxvkq instruction matheus.ferst
2021-10-23 21:29   ` Richard Henderson
2021-10-22  2:06 ` [PATCH 00/33] PowerISA v3.1 instruction batch Richard Henderson
2021-10-22 11:13   ` Matheus K. Ferst

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