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From: matheus.ferst@eldorado.org.br
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: lucas.castro@eldorado.org.br, richard.henderson@linaro.org,
	groug@kaod.org, luis.pires@eldorado.org.br,
	matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au
Subject: [PATCH 17/33] target/ppc: Implement Vector Insert from VSR using GPR index insns
Date: Thu, 21 Oct 2021 16:45:31 -0300	[thread overview]
Message-ID: <20211021194547.672988-18-matheus.ferst@eldorado.org.br> (raw)
In-Reply-To: <20211021194547.672988-1-matheus.ferst@eldorado.org.br>

From: Matheus Ferst <matheus.ferst@eldorado.org.br>

Implements the following PowerISA v3.1 instructions:
vinsbvlx: Vector Insert Byte from VSR using GPR-specified Left-Index
vinshvlx: Vector Insert Halfword from VSR using GPR-specified
          Left-Index
vinswvlx: Vector Insert Word from VSR using GPR-specified Left-Index
vinsbvrx: Vector Insert Byte from VSR using GPR-specified Right-Index
vinshvrx: Vector Insert Halfword from VSR using GPR-specified
          Right-Index
vinswvrx: Vector Insert Word from VSR using GPR-specified Right-Index

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
 target/ppc/insn32.decode            |  7 +++++++
 target/ppc/int_helper.c             |  6 +++---
 target/ppc/translate/vmx-impl.c.inc | 32 +++++++++++++++++++++++++++++
 3 files changed, 42 insertions(+), 3 deletions(-)

diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index e1f76aac34..de410abf7d 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -359,5 +359,12 @@ VINSDRX         000100 ..... ..... ..... 01111001111    @VX
 VINSW           000100 ..... - .... ..... 00011001111   @VX_uim4
 VINSD           000100 ..... - .... ..... 00111001111   @VX_uim4
 
+VINSBVLX        000100 ..... ..... ..... 00000001111    @VX
+VINSBVRX        000100 ..... ..... ..... 00100001111    @VX
+VINSHVLX        000100 ..... ..... ..... 00001001111    @VX
+VINSHVRX        000100 ..... ..... ..... 00101001111    @VX
+VINSWVLX        000100 ..... ..... ..... 00010001111    @VX
+VINSWVRX        000100 ..... ..... ..... 00110001111    @VX
+
 VSLDBI          000100 ..... ..... ..... 00 ... 010110  @VN
 VSRDBI          000100 ..... ..... ..... 01 ... 010110  @VN
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 63263dd912..0506358ad8 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1683,9 +1683,9 @@ void glue(glue(helper_VINS, SUFFIX), LX)(CPUPPCState *env, ppc_avr_t *t,       \
     if (idx < 0 || idx > maxidx) {                                             \
         char c = idx < 0 ? 'R' : 'L';                                          \
         idx =  idx < 0 ? sizeof(TYPE) - idx : idx;                             \
-        qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for VINS" #SUFFIX "%cX"  \
-                      " at 0x" TARGET_FMT_lx ", RA = " TARGET_FMT_ld " > %d\n",\
-                      c, env->nip, idx, maxidx);                               \
+        qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for VINS" #SUFFIX "%cX/" \
+                      "VINS" #SUFFIX "V%cX at 0x" TARGET_FMT_lx ", RA = "      \
+                      TARGET_FMT_ld " > %d\n", c, c, env->nip, idx, maxidx);   \
     } else {                                                                   \
         *(TYPE *)ELEM_ADDR(t, idx, sizeof(TYPE)) = (TYPE)val;                  \
     }                                                                          \
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 3b526977e4..03327d3fe4 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1260,6 +1260,20 @@ static bool do_vinsx(DisasContext *ctx, int vrt, int size, bool right, TCGv ra,
     return true;
 }
 
+static bool do_vinsvx(DisasContext *ctx, int vrt, int size, bool right, TCGv ra,
+                int vrb, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
+{
+    bool ok;
+    TCGv_i64 val;
+
+    val = tcg_temp_new_i64();
+    get_avr64(val, vrb, true);
+    ok = do_vinsx(ctx, vrt, size, right, ra, val, gen_helper);
+
+    tcg_temp_free_i64(val);
+    return ok;
+}
+
 static bool do_vinsx_VX(DisasContext *ctx, arg_VX *a, int size, bool right,
                         void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
 {
@@ -1283,6 +1297,16 @@ static bool do_vinsx_VX(DisasContext *ctx, arg_VX *a, int size, bool right,
 #endif
 }
 
+static bool do_vinsvx_VX(DisasContext *ctx, arg_VX *a, int size, bool right,
+                        void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
+{
+    REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+    REQUIRE_VECTOR(ctx);
+
+    return do_vinsvx(ctx, a->vrt, size, right, cpu_gpr[a->vra], a->vrb,
+                     gen_helper);
+}
+
 static bool do_vins_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size,
                         void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
 {
@@ -1327,6 +1351,14 @@ TRANS(VINSDRX, do_vinsx_VX, 8, true, gen_helper_VINSDLX)
 TRANS(VINSW, do_vins_VX_uim4, 4, gen_helper_VINSWLX)
 TRANS(VINSD, do_vins_VX_uim4, 8, gen_helper_VINSDLX)
 
+TRANS(VINSBVLX, do_vinsvx_VX, 1, false, gen_helper_VINSBLX)
+TRANS(VINSHVLX, do_vinsvx_VX, 2, false, gen_helper_VINSHLX)
+TRANS(VINSWVLX, do_vinsvx_VX, 4, false, gen_helper_VINSWLX)
+
+TRANS(VINSBVRX, do_vinsvx_VX, 1, true, gen_helper_VINSBLX)
+TRANS(VINSHVRX, do_vinsvx_VX, 2, true, gen_helper_VINSHLX)
+TRANS(VINSWVRX, do_vinsvx_VX, 4, true, gen_helper_VINSWLX)
+
 static void gen_vsldoi(DisasContext *ctx)
 {
     TCGv_ptr ra, rb, rd;
-- 
2.25.1



  parent reply	other threads:[~2021-10-21 20:10 UTC|newest]

Thread overview: 84+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-21 19:45 [PATCH 00/33] PowerISA v3.1 instruction batch matheus.ferst
2021-10-21 19:45 ` [PATCH 01/33] target/ppc: introduce do_ea_calc matheus.ferst
2021-10-22 21:51   ` Richard Henderson
2021-10-22 21:57   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 02/33] target/ppc: move resolve_PLS_D to translate.c matheus.ferst
2021-10-22 22:01   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 03/33] target/ppc: Move load and store floating point instructions to decodetree matheus.ferst
2021-10-22 22:19   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 04/33] target/ppc: Implement PLFS, PLFD, PSTFS and PSTFD instructions matheus.ferst
2021-10-22 22:24   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 05/33] target/ppc: Move LQ and STQ to decodetree matheus.ferst
2021-10-22 22:53   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 06/33] target/ppc: Implement PLQ and PSTQ matheus.ferst
2021-10-22 22:54   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 07/33] target/ppc: Implement cntlzdm matheus.ferst
2021-10-22 23:16   ` Richard Henderson
2021-10-26 14:33     ` Matheus K. Ferst
2021-10-21 19:45 ` [PATCH 08/33] target/ppc: Implement cnttzdm matheus.ferst
2021-10-22 23:55   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 09/33] target/ppc: Implement pdepd instruction matheus.ferst
2021-10-23  0:04   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 10/33] target/ppc: Implement pextd instruction matheus.ferst
2021-10-23  0:26   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 11/33] target/ppc: Move vcfuged to vmx-impl.c.inc matheus.ferst
2021-10-23  0:31   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 12/33] target/ppc: Implement vclzdm/vctzdm instructions matheus.ferst
2021-10-23  0:34   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 13/33] target/ppc: Implement vpdepd/vpextd instruction matheus.ferst
2021-10-23  0:38   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 14/33] target/ppc: Implement vsldbi/vsrdbi instructions matheus.ferst
2021-10-23  4:07   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 15/33] target/ppc: Implement Vector Insert from GPR using GPR index insns matheus.ferst
2021-10-23  4:37   ` Richard Henderson
2021-10-23  4:40   ` Richard Henderson
2021-10-23 10:12     ` BALATON Zoltan
2021-10-23 18:36       ` Richard Henderson
2021-10-23 20:02         ` BALATON Zoltan
2021-10-23 20:09           ` Richard Henderson
2021-10-26 14:33     ` Matheus K. Ferst
2021-10-21 19:45 ` [PATCH 16/33] target/ppc: Implement Vector Insert Word from GPR using Immediate insns matheus.ferst
2021-10-23  4:42   ` Richard Henderson
2021-10-26 14:33     ` Matheus K. Ferst
2021-10-26 16:58       ` Richard Henderson
2021-10-26 18:45         ` Paul A. Clarke
2021-10-27 11:49           ` Matheus K. Ferst
2021-10-21 19:45 ` matheus.ferst [this message]
2021-10-23  4:48   ` [PATCH 17/33] target/ppc: Implement Vector Insert from VSR using GPR index insns Richard Henderson
2021-10-23  4:54   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 18/33] target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree matheus.ferst
2021-10-23  4:53   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 19/33] target/ppc: Implement Vector Extract Double to VSR using GPR index insns matheus.ferst
2021-10-23 20:01   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 20/33] target/ppc: Introduce REQUIRE_VSX macro matheus.ferst
2021-10-23 20:10   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 21/33] target/ppc: moved stxv and lxv from legacy to decodtree matheus.ferst
2021-10-23 20:34   ` Richard Henderson
2021-10-23 20:39     ` Richard Henderson
2021-10-23 20:46   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 22/33] target/ppc: moved stxvx and lxvx " matheus.ferst
2021-10-23 20:38   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 23/33] target/ppc: added the instructions LXVP and STXVP matheus.ferst
2021-10-23 20:48   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 24/33] target/ppc: added the instructions LXVPX and STXVPX matheus.ferst
2021-10-23 20:49   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 25/33] target/ppc: added the instructions PLXV and PSTXV matheus.ferst
2021-10-23 20:56   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 26/33] target/ppc: added the instructions PLXVP and PSTXVP matheus.ferst
2021-10-23 20:57   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 27/33] target/ppc: moved XXSPLTW to using decodetree matheus.ferst
2021-10-23 21:03   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 28/33] target/ppc: moved XXSPLTIB " matheus.ferst
2021-10-23 21:06   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 29/33] target/ppc: implemented XXSPLTI32DX matheus.ferst
2021-10-23 21:12   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 30/33] target/ppc: Implemented XXSPLTIW using decodetree matheus.ferst
2021-10-23 21:15   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 31/33] target/ppc: implemented XXSPLTIDP instruction matheus.ferst
2021-10-23 21:19   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 32/33] target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions matheus.ferst
2021-10-23 21:24   ` Richard Henderson
2021-10-21 19:45 ` [PATCH 33/33] target/ppc: Implement lxvkq instruction matheus.ferst
2021-10-23 21:29   ` Richard Henderson
2021-10-22  2:06 ` [PATCH 00/33] PowerISA v3.1 instruction batch Richard Henderson
2021-10-22 11:13   ` Matheus K. Ferst

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