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* [RFC PATCH 0/9] clk/mmc: renesas_sdhi: refactor SDnH to be a seperate clock
@ 2021-09-28 20:07 Wolfram Sang
  2021-09-28 20:07 ` [RFC PATCH 1/9] clk: renesas: gen3-cpg: add dummy SDnH clock Wolfram Sang
                   ` (8 more replies)
  0 siblings, 9 replies; 21+ messages in thread
From: Wolfram Sang @ 2021-09-28 20:07 UTC (permalink / raw)
  To: linux-renesas-soc
  Cc: linux-clk, linux-mmc, Geert Uytterhoeven, Yoshihiro Shimoda,
	Wolfram Sang

We wanted this for a long time, so finally here is the first RFC to
refactor SDHI clocks so that SDnH is a seperate clock. In general, the
new code looks much clearer to me, plus it is 80 lines shorter.

One downside is that patch 4 looks messy. When switching from old to new
handling in the clock driver, I see no alternative to switch the MMC
driver in the same patch. clk_set_rate just has to work. However, the
MMC part is small, so I hope we can deal with it as an exception this
time. Please read the patch description for details.

Another thing to discuss is the gating of SDn and SDnH. Documentation
says that SDnH should be gated/ungated depending on the selected
frequency, not depending on the number of users. I tried to handle this
via RuntimePM but its need to balance enable/disable calls added quite
some complexity to my prototype, and it was far from working. So, I
switched strategies and included the gating to the divider table. So,
for every divider, SDnH is correctly gated/ungated. SDn should be always
on, so this is handled there as well. If we want to save power, I think
we can still use RuntimePM to disable all clocks, as long as we make
sure the frequencies are set again when resuming. However, this all is
not a regression because RuntimePM currently does not work for SDHI
anyhow.

The third thing to discuss is probably the DT bindings. I just added DT
updates for R-Car H3 ES2.0 and M3-N, but will happily add the others
once we agreed on the bindings.

These patches have been tested on R-Car H3 ES2.0, M3N, and V3U. More
testing is needed on Gen2 to make sure no regressions happen. The base
branch is <renesas-devel-2021-09-28-v5.15-rc3>. A branch can be found
here:

git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git renesas/sdhi/separate-sdhn

Hopefully I haven't forgotten something important, but I think this is
it for now.

Looking forward to comments and testing.

Thanks and happy hacking,

   Wolfram


Wolfram Sang (9):
  clk: renesas: gen3-cpg: add dummy SDnH clock
  clk: renesas: add SDnH clock to Gen3 SoCs
  clk: renesas: r8a779a0: add SDnH clock to V3U
  clk: renesas: gen3: switch to new SD clock handling
  clk: renesas: gen3-cpg: remove outdated SD_SKIP_FIRST
  dt-bindings: mmc: renesas,sdhi: add optional SDnH clock
  arm64: dts: r8a77951: add SDnH clocks
  arm64: dts: r8a77965: add SDnH clocks
  mmc: renesas_sdhi: parse DT for SDnH

 .../devicetree/bindings/mmc/renesas,sdhi.yaml |   3 +-
 arch/arm64/boot/dts/renesas/r8a77951.dtsi     |  12 +-
 arch/arm64/boot/dts/renesas/r8a77965.dtsi     |  12 +-
 drivers/clk/renesas/r8a774a1-cpg-mssr.c       |  12 +-
 drivers/clk/renesas/r8a774b1-cpg-mssr.c       |  12 +-
 drivers/clk/renesas/r8a774c0-cpg-mssr.c       |   9 +-
 drivers/clk/renesas/r8a774e1-cpg-mssr.c       |  12 +-
 drivers/clk/renesas/r8a7795-cpg-mssr.c        |  12 +-
 drivers/clk/renesas/r8a7796-cpg-mssr.c        |  12 +-
 drivers/clk/renesas/r8a77965-cpg-mssr.c       |  12 +-
 drivers/clk/renesas/r8a77980-cpg-mssr.c       |   3 +-
 drivers/clk/renesas/r8a77990-cpg-mssr.c       |   9 +-
 drivers/clk/renesas/r8a77995-cpg-mssr.c       |   3 +-
 drivers/clk/renesas/r8a779a0-cpg-mssr.c       |  17 +-
 drivers/clk/renesas/rcar-cpg-lib.c            | 211 +++---------------
 drivers/clk/renesas/rcar-cpg-lib.h            |   7 +-
 drivers/clk/renesas/rcar-gen3-cpg.c           |  24 +-
 drivers/clk/renesas/rcar-gen3-cpg.h           |   4 +
 drivers/mmc/host/renesas_sdhi.h               |   1 +
 drivers/mmc/host/renesas_sdhi_core.c          |  36 ++-
 20 files changed, 170 insertions(+), 253 deletions(-)

-- 
2.30.2


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [RFC PATCH 1/9] clk: renesas: gen3-cpg: add dummy SDnH clock
  2021-09-28 20:07 [RFC PATCH 0/9] clk/mmc: renesas_sdhi: refactor SDnH to be a seperate clock Wolfram Sang
@ 2021-09-28 20:07 ` Wolfram Sang
  2021-10-11 18:03   ` Geert Uytterhoeven
  2021-09-28 20:07 ` [RFC PATCH 2/9] clk: renesas: add SDnH clock to Gen3 SoCs Wolfram Sang
                   ` (7 subsequent siblings)
  8 siblings, 1 reply; 21+ messages in thread
From: Wolfram Sang @ 2021-09-28 20:07 UTC (permalink / raw)
  To: linux-renesas-soc
  Cc: linux-clk, linux-mmc, Geert Uytterhoeven, Yoshihiro Shimoda,
	Wolfram Sang

Currently, SDnH is handled together with SDn. This caused lots of
problems, so we want SDnH as a seperate clock. Introduce a dummy SDnH
type here which creates a fixed-factor clock with factor 1. That allows
us to convert the per-SoC CPG drivers while keeping the old behaviour
for now. A later patch then will add the proper functionality.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 drivers/clk/renesas/rcar-cpg-lib.c  | 9 +++++++++
 drivers/clk/renesas/rcar-cpg-lib.h  | 4 ++++
 drivers/clk/renesas/rcar-gen3-cpg.c | 4 ++++
 drivers/clk/renesas/rcar-gen3-cpg.h | 4 ++++
 4 files changed, 21 insertions(+)

diff --git a/drivers/clk/renesas/rcar-cpg-lib.c b/drivers/clk/renesas/rcar-cpg-lib.c
index 5678768ee1f2..351cb9c04f5c 100644
--- a/drivers/clk/renesas/rcar-cpg-lib.c
+++ b/drivers/clk/renesas/rcar-cpg-lib.c
@@ -65,6 +65,15 @@ void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
 /*
  * SDn Clock
  */
+
+struct clk * __init cpg_sdh_clk_register(const char *name,
+	void __iomem *sdnckcr, const char *parent_name,
+	struct raw_notifier_head *notifiers)
+{
+	/* placeholder during transition */
+	return clk_register_fixed_factor(NULL, name, parent_name, 0, 1, 1);
+}
+
 #define CPG_SD_STP_HCK		BIT(9)
 #define CPG_SD_STP_CK		BIT(8)
 
diff --git a/drivers/clk/renesas/rcar-cpg-lib.h b/drivers/clk/renesas/rcar-cpg-lib.h
index d00c91b116ca..548cb9562f35 100644
--- a/drivers/clk/renesas/rcar-cpg-lib.h
+++ b/drivers/clk/renesas/rcar-cpg-lib.h
@@ -26,6 +26,10 @@ void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
 
 void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set);
 
+struct clk * __init cpg_sdh_clk_register(const char *name,
+	void __iomem *sdnckcr, const char *parent_name,
+	struct raw_notifier_head *notifiers);
+
 struct clk * __init cpg_sd_clk_register(const char *name,
 	void __iomem *base, unsigned int offset, const char *parent_name,
 	struct raw_notifier_head *notifiers, bool skip_first);
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 558191c99b48..182b189bc8f4 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -486,6 +486,10 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
 			mult *= 2;
 		break;
 
+	case CLK_TYPE_GEN3_SDH:
+		return cpg_sdh_clk_register(core->name, base + core->offset,
+					   __clk_get_name(parent), notifiers);
+
 	case CLK_TYPE_GEN3_SD:
 		return cpg_sd_clk_register(core->name, base, core->offset,
 					   __clk_get_name(parent), notifiers,
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index 3d949c4a3244..2bc0afadf604 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -17,6 +17,7 @@ enum rcar_gen3_clk_types {
 	CLK_TYPE_GEN3_PLL2,
 	CLK_TYPE_GEN3_PLL3,
 	CLK_TYPE_GEN3_PLL4,
+	CLK_TYPE_GEN3_SDH,
 	CLK_TYPE_GEN3_SD,
 	CLK_TYPE_GEN3_R,
 	CLK_TYPE_GEN3_MDSEL,	/* Select parent/divider using mode pin */
@@ -32,6 +33,9 @@ enum rcar_gen3_clk_types {
 	CLK_TYPE_GEN3_SOC_BASE,
 };
 
+#define DEF_GEN3_SDH(_name, _id, _parent, _offset)	\
+	DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset)
+
 #define DEF_GEN3_SD(_name, _id, _parent, _offset)	\
 	DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
 
-- 
2.30.2


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [RFC PATCH 2/9] clk: renesas: add SDnH clock to Gen3 SoCs
  2021-09-28 20:07 [RFC PATCH 0/9] clk/mmc: renesas_sdhi: refactor SDnH to be a seperate clock Wolfram Sang
  2021-09-28 20:07 ` [RFC PATCH 1/9] clk: renesas: gen3-cpg: add dummy SDnH clock Wolfram Sang
@ 2021-09-28 20:07 ` Wolfram Sang
  2021-10-11 18:03   ` Geert Uytterhoeven
  2021-09-28 20:07 ` [RFC PATCH 3/9] clk: renesas: r8a779a0: add SDnH clock to V3U Wolfram Sang
                   ` (6 subsequent siblings)
  8 siblings, 1 reply; 21+ messages in thread
From: Wolfram Sang @ 2021-09-28 20:07 UTC (permalink / raw)
  To: linux-renesas-soc
  Cc: linux-clk, linux-mmc, Geert Uytterhoeven, Yoshihiro Shimoda,
	Wolfram Sang

Currently a pass-through clock but we will make it a real divider clock
in the next patches.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 drivers/clk/renesas/r8a774a1-cpg-mssr.c | 12 ++++++++----
 drivers/clk/renesas/r8a774b1-cpg-mssr.c | 12 ++++++++----
 drivers/clk/renesas/r8a774c0-cpg-mssr.c |  9 ++++++---
 drivers/clk/renesas/r8a774e1-cpg-mssr.c | 12 ++++++++----
 drivers/clk/renesas/r8a7795-cpg-mssr.c  | 12 ++++++++----
 drivers/clk/renesas/r8a7796-cpg-mssr.c  | 12 ++++++++----
 drivers/clk/renesas/r8a77965-cpg-mssr.c | 12 ++++++++----
 drivers/clk/renesas/r8a77980-cpg-mssr.c |  3 ++-
 drivers/clk/renesas/r8a77990-cpg-mssr.c |  9 ++++++---
 drivers/clk/renesas/r8a77995-cpg-mssr.c |  3 ++-
 10 files changed, 64 insertions(+), 32 deletions(-)

diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index 39b185d8e957..804f3362763c 100644
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -100,10 +100,14 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
 	DEF_FIXED("s3d2",       R8A774A1_CLK_S3D2,  CLK_S3,         2, 1),
 	DEF_FIXED("s3d4",       R8A774A1_CLK_S3D4,  CLK_S3,         4, 1),
 
-	DEF_GEN3_SD("sd0",      R8A774A1_CLK_SD0,   CLK_SDSRC,     0x074),
-	DEF_GEN3_SD("sd1",      R8A774A1_CLK_SD1,   CLK_SDSRC,     0x078),
-	DEF_GEN3_SD("sd2",      R8A774A1_CLK_SD2,   CLK_SDSRC,     0x268),
-	DEF_GEN3_SD("sd3",      R8A774A1_CLK_SD3,   CLK_SDSRC,     0x26c),
+	DEF_GEN3_SDH("sd0h",    R8A774A1_CLK_SD0H,  CLK_SDSRC,        0x074),
+	DEF_GEN3_SD( "sd0",     R8A774A1_CLK_SD0,   R8A774A1_CLK_SD0H, 0x074),
+	DEF_GEN3_SDH("sd1h",    R8A774A1_CLK_SD1H,  CLK_SDSRC,        0x078),
+	DEF_GEN3_SD( "sd1",     R8A774A1_CLK_SD1,   R8A774A1_CLK_SD1H, 0x078),
+	DEF_GEN3_SDH("sd2h",    R8A774A1_CLK_SD2H,  CLK_SDSRC,        0x268),
+	DEF_GEN3_SD( "sd2",     R8A774A1_CLK_SD2,   R8A774A1_CLK_SD2H, 0x268),
+	DEF_GEN3_SDH("sd3h",    R8A774A1_CLK_SD3H,  CLK_SDSRC,        0x26c),
+	DEF_GEN3_SD( "sd3",     R8A774A1_CLK_SD3,   R8A774A1_CLK_SD3H, 0x26c),
 
 	DEF_FIXED("cl",         R8A774A1_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
 	DEF_FIXED("cp",         R8A774A1_CLK_CP,    CLK_EXTAL,      2, 1),
diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
index af602d83c8ce..97fe5d2227fe 100644
--- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
@@ -97,10 +97,14 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = {
 	DEF_FIXED("s3d2",       R8A774B1_CLK_S3D2,  CLK_S3,         2, 1),
 	DEF_FIXED("s3d4",       R8A774B1_CLK_S3D4,  CLK_S3,         4, 1),
 
-	DEF_GEN3_SD("sd0",      R8A774B1_CLK_SD0,   CLK_SDSRC,     0x074),
-	DEF_GEN3_SD("sd1",      R8A774B1_CLK_SD1,   CLK_SDSRC,     0x078),
-	DEF_GEN3_SD("sd2",      R8A774B1_CLK_SD2,   CLK_SDSRC,     0x268),
-	DEF_GEN3_SD("sd3",      R8A774B1_CLK_SD3,   CLK_SDSRC,     0x26c),
+	DEF_GEN3_SDH("sd0h",    R8A774B1_CLK_SD0H,  CLK_SDSRC,         0x074),
+	DEF_GEN3_SD( "sd0",     R8A774B1_CLK_SD0,   R8A774B1_CLK_SD0H, 0x074),
+	DEF_GEN3_SDH("sd1h",    R8A774B1_CLK_SD1H,  CLK_SDSRC,         0x078),
+	DEF_GEN3_SD( "sd1",     R8A774B1_CLK_SD1,   R8A774B1_CLK_SD1H, 0x078),
+	DEF_GEN3_SDH("sd2h",    R8A774B1_CLK_SD2H,  CLK_SDSRC,         0x268),
+	DEF_GEN3_SD( "sd2",     R8A774B1_CLK_SD2,   R8A774B1_CLK_SD2H, 0x268),
+	DEF_GEN3_SDH("sd3h",    R8A774B1_CLK_SD3H,  CLK_SDSRC,         0x26c),
+	DEF_GEN3_SD( "sd3",     R8A774B1_CLK_SD3,   R8A774B1_CLK_SD3H, 0x26c),
 
 	DEF_FIXED("cl",         R8A774B1_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
 	DEF_FIXED("cp",         R8A774B1_CLK_CP,    CLK_EXTAL,      2, 1),
diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index 5b938eb2df25..611a5bd8f29e 100644
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -108,9 +108,12 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = {
 	DEF_FIXED("s3d2",      R8A774C0_CLK_S3D2,  CLK_S3,         2, 1),
 	DEF_FIXED("s3d4",      R8A774C0_CLK_S3D4,  CLK_S3,         4, 1),
 
-	DEF_GEN3_SD("sd0",     R8A774C0_CLK_SD0,   CLK_SDSRC,	  0x0074),
-	DEF_GEN3_SD("sd1",     R8A774C0_CLK_SD1,   CLK_SDSRC,	  0x0078),
-	DEF_GEN3_SD("sd3",     R8A774C0_CLK_SD3,   CLK_SDSRC,	  0x026c),
+	DEF_GEN3_SDH("sd0h",   R8A774C0_CLK_SD0H, CLK_SDSRC,   	     0x0074),
+	DEF_GEN3_SD( "sd0",    R8A774C0_CLK_SD0,  R8A774C0_CLK_SD0H, 0x0074),
+	DEF_GEN3_SDH("sd1h",   R8A774C0_CLK_SD1H, CLK_SDSRC,         0x0078),
+	DEF_GEN3_SD( "sd1",    R8A774C0_CLK_SD1,  R8A774C0_CLK_SD1H, 0x0078),
+	DEF_GEN3_SDH("sd3h",   R8A774C0_CLK_SD3H, CLK_SDSRC,         0x026c),
+	DEF_GEN3_SD( "sd3",    R8A774C0_CLK_SD3,  R8A774C0_CLK_SD3H, 0x026c),
 
 	DEF_FIXED("cl",        R8A774C0_CLK_CL,    CLK_PLL1,      48, 1),
 	DEF_FIXED("cp",        R8A774C0_CLK_CP,    CLK_EXTAL,      2, 1),
diff --git a/drivers/clk/renesas/r8a774e1-cpg-mssr.c b/drivers/clk/renesas/r8a774e1-cpg-mssr.c
index 40c71466df37..98beea6f4f6c 100644
--- a/drivers/clk/renesas/r8a774e1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774e1-cpg-mssr.c
@@ -100,10 +100,14 @@ static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = {
 	DEF_FIXED("s3d2",       R8A774E1_CLK_S3D2,  CLK_S3,         2, 1),
 	DEF_FIXED("s3d4",       R8A774E1_CLK_S3D4,  CLK_S3,         4, 1),
 
-	DEF_GEN3_SD("sd0",      R8A774E1_CLK_SD0,   CLK_SDSRC,     0x074),
-	DEF_GEN3_SD("sd1",      R8A774E1_CLK_SD1,   CLK_SDSRC,     0x078),
-	DEF_GEN3_SD("sd2",      R8A774E1_CLK_SD2,   CLK_SDSRC,     0x268),
-	DEF_GEN3_SD("sd3",      R8A774E1_CLK_SD3,   CLK_SDSRC,     0x26c),
+	DEF_GEN3_SDH("sd0h",    R8A774E1_CLK_SD0H,  CLK_SDSRC,         0x074),
+	DEF_GEN3_SD( "sd0",     R8A774E1_CLK_SD0,   R8A774E1_CLK_SD0H, 0x074),
+	DEF_GEN3_SDH("sd1h",    R8A774E1_CLK_SD1H,  CLK_SDSRC,         0x078),
+	DEF_GEN3_SD( "sd1",     R8A774E1_CLK_SD1,   R8A774E1_CLK_SD1H, 0x078),
+	DEF_GEN3_SDH("sd2h",    R8A774E1_CLK_SD2H,  CLK_SDSRC,         0x268),
+	DEF_GEN3_SD( "sd2",     R8A774E1_CLK_SD2,   R8A774E1_CLK_SD2H, 0x268),
+	DEF_GEN3_SDH("sd3h",    R8A774E1_CLK_SD3H,  CLK_SDSRC,         0x26c),
+	DEF_GEN3_SD( "sd3",     R8A774E1_CLK_SD3,   R8A774E1_CLK_SD3H, 0x26c),
 
 	DEF_FIXED("cl",         R8A774E1_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
 	DEF_FIXED("cr",         R8A774E1_CLK_CR,    CLK_PLL1_DIV4,  2, 1),
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index c32d2c678046..9ca26057e809 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -104,10 +104,14 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
 	DEF_FIXED("s3d2",       R8A7795_CLK_S3D2,  CLK_S3,         2, 1),
 	DEF_FIXED("s3d4",       R8A7795_CLK_S3D4,  CLK_S3,         4, 1),
 
-	DEF_GEN3_SD("sd0",      R8A7795_CLK_SD0,   CLK_SDSRC,     0x074),
-	DEF_GEN3_SD("sd1",      R8A7795_CLK_SD1,   CLK_SDSRC,     0x078),
-	DEF_GEN3_SD("sd2",      R8A7795_CLK_SD2,   CLK_SDSRC,     0x268),
-	DEF_GEN3_SD("sd3",      R8A7795_CLK_SD3,   CLK_SDSRC,     0x26c),
+	DEF_GEN3_SDH("sd0h",    R8A7795_CLK_SD0H,  CLK_SDSRC,        0x074),
+	DEF_GEN3_SD( "sd0",     R8A7795_CLK_SD0,   R8A7795_CLK_SD0H, 0x074),
+	DEF_GEN3_SDH("sd1h",    R8A7795_CLK_SD1H,  CLK_SDSRC,        0x078),
+	DEF_GEN3_SD( "sd1",     R8A7795_CLK_SD1,   R8A7795_CLK_SD1H, 0x078),
+	DEF_GEN3_SDH("sd2h",    R8A7795_CLK_SD2H,  CLK_SDSRC,        0x268),
+	DEF_GEN3_SD( "sd2",     R8A7795_CLK_SD2,   R8A7795_CLK_SD2H, 0x268),
+	DEF_GEN3_SDH("sd3h",    R8A7795_CLK_SD3H,  CLK_SDSRC,        0x26c),
+	DEF_GEN3_SD( "sd3",     R8A7795_CLK_SD3,   R8A7795_CLK_SD3H, 0x26c),
 
 	DEF_FIXED("cl",         R8A7795_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
 	DEF_FIXED("cr",         R8A7795_CLK_CR,    CLK_PLL1_DIV4,  2, 1),
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 41593c126faf..0dc0ba349a54 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -106,10 +106,14 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
 	DEF_FIXED("s3d2",       R8A7796_CLK_S3D2,  CLK_S3,         2, 1),
 	DEF_FIXED("s3d4",       R8A7796_CLK_S3D4,  CLK_S3,         4, 1),
 
-	DEF_GEN3_SD("sd0",      R8A7796_CLK_SD0,   CLK_SDSRC,     0x074),
-	DEF_GEN3_SD("sd1",      R8A7796_CLK_SD1,   CLK_SDSRC,     0x078),
-	DEF_GEN3_SD("sd2",      R8A7796_CLK_SD2,   CLK_SDSRC,     0x268),
-	DEF_GEN3_SD("sd3",      R8A7796_CLK_SD3,   CLK_SDSRC,     0x26c),
+	DEF_GEN3_SDH("sd0h",    R8A7796_CLK_SD0H,  CLK_SDSRC,        0x074),
+	DEF_GEN3_SD( "sd0",     R8A7796_CLK_SD0,   R8A7796_CLK_SD0H, 0x074),
+	DEF_GEN3_SDH("sd1h",    R8A7796_CLK_SD1H,  CLK_SDSRC,        0x078),
+	DEF_GEN3_SD( "sd1",     R8A7796_CLK_SD1,   R8A7796_CLK_SD1H, 0x078),
+	DEF_GEN3_SDH("sd2h",    R8A7796_CLK_SD2H,  CLK_SDSRC,        0x268),
+	DEF_GEN3_SD( "sd2",     R8A7796_CLK_SD2,   R8A7796_CLK_SD2H, 0x268),
+	DEF_GEN3_SDH("sd3h",    R8A7796_CLK_SD3H,  CLK_SDSRC,        0x26c),
+	DEF_GEN3_SD( "sd3",     R8A7796_CLK_SD3,   R8A7796_CLK_SD3H, 0x26c),
 
 	DEF_FIXED("cl",         R8A7796_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
 	DEF_FIXED("cr",         R8A7796_CLK_CR,    CLK_PLL1_DIV4,  2, 1),
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index bc1be8bcbbe4..d85489522b8e 100644
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -101,10 +101,14 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
 	DEF_FIXED("s3d2",	R8A77965_CLK_S3D2,	CLK_S3,		2, 1),
 	DEF_FIXED("s3d4",	R8A77965_CLK_S3D4,	CLK_S3,		4, 1),
 
-	DEF_GEN3_SD("sd0",	R8A77965_CLK_SD0,	CLK_SDSRC,	0x074),
-	DEF_GEN3_SD("sd1",	R8A77965_CLK_SD1,	CLK_SDSRC,	0x078),
-	DEF_GEN3_SD("sd2",	R8A77965_CLK_SD2,	CLK_SDSRC,	0x268),
-	DEF_GEN3_SD("sd3",	R8A77965_CLK_SD3,	CLK_SDSRC,	0x26c),
+	DEF_GEN3_SDH("sd0h",	R8A77965_CLK_SD0H,	CLK_SDSRC,   	   0x074),
+	DEF_GEN3_SD( "sd0",	R8A77965_CLK_SD0,	R8A77965_CLK_SD0H, 0x074),
+	DEF_GEN3_SDH("sd1h",	R8A77965_CLK_SD1H,	CLK_SDSRC,   	   0x078),
+	DEF_GEN3_SD( "sd1",	R8A77965_CLK_SD1,	R8A77965_CLK_SD1H, 0x078),
+	DEF_GEN3_SDH("sd2h",	R8A77965_CLK_SD2H,	CLK_SDSRC,   	   0x268),
+	DEF_GEN3_SD( "sd2",	R8A77965_CLK_SD2,	R8A77965_CLK_SD2H, 0x268),
+	DEF_GEN3_SDH("sd3h",	R8A77965_CLK_SD3H,	CLK_SDSRC,   	   0x26c),
+	DEF_GEN3_SD( "sd3",	R8A77965_CLK_SD3,	R8A77965_CLK_SD3H, 0x26c),
 
 	DEF_FIXED("cl",		R8A77965_CLK_CL,	CLK_PLL1_DIV2, 48, 1),
 	DEF_FIXED("cr",         R8A77965_CLK_CR,	CLK_PLL1_DIV4,  2, 1),
diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c
index 9fe372286c1e..4ff2abad1de0 100644
--- a/drivers/clk/renesas/r8a77980-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c
@@ -96,7 +96,8 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = {
 	DEF_FIXED("s3d2",	R8A77980_CLK_S3D2,  CLK_S3,         2, 1),
 	DEF_FIXED("s3d4",	R8A77980_CLK_S3D4,  CLK_S3,         4, 1),
 
-	DEF_GEN3_SD("sd0",	R8A77980_CLK_SD0,   CLK_SDSRC,	  0x0074),
+	DEF_GEN3_SDH("sd0h",	R8A77980_CLK_SD0H,  CLK_SDSRC,	       0x0074),
+	DEF_GEN3_SD( "sd0",	R8A77980_CLK_SD0,   R8A77980_CLK_SD0H, 0x0074),
 
 	DEF_FIXED("cl",		R8A77980_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
 	DEF_FIXED("cp",		R8A77980_CLK_CP,    CLK_EXTAL,	    2, 1),
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index a582f2ec3294..637c3f062fae 100644
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -100,9 +100,12 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
 	DEF_FIXED("s3d2",      R8A77990_CLK_S3D2,  CLK_S3,         2, 1),
 	DEF_FIXED("s3d4",      R8A77990_CLK_S3D4,  CLK_S3,         4, 1),
 
-	DEF_GEN3_SD("sd0",     R8A77990_CLK_SD0,   CLK_SDSRC,	  0x0074),
-	DEF_GEN3_SD("sd1",     R8A77990_CLK_SD1,   CLK_SDSRC,	  0x0078),
-	DEF_GEN3_SD("sd3",     R8A77990_CLK_SD3,   CLK_SDSRC,	  0x026c),
+	DEF_GEN3_SDH("sd0h",   R8A77990_CLK_SD0H,  CLK_SDSRC,         0x0074),
+	DEF_GEN3_SD( "sd0",    R8A77990_CLK_SD0,   R8A77990_CLK_SD0H, 0x0074),
+	DEF_GEN3_SDH("sd1h",   R8A77990_CLK_SD1H,  CLK_SDSRC,         0x0078),
+	DEF_GEN3_SD( "sd1",    R8A77990_CLK_SD1,   R8A77990_CLK_SD1H, 0x0078),
+	DEF_GEN3_SDH("sd3h",   R8A77990_CLK_SD3H,  CLK_SDSRC,         0x026c),
+	DEF_GEN3_SD( "sd3",    R8A77990_CLK_SD3,   R8A77990_CLK_SD3H, 0x026c),
 
 	DEF_FIXED("cl",        R8A77990_CLK_CL,    CLK_PLL1,      48, 1),
 	DEF_FIXED("cr",        R8A77990_CLK_CR,    CLK_PLL1D2,     2, 1),
diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
index 81c0bc1e78af..007f6fda1db4 100644
--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -103,7 +103,8 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
 	DEF_GEN3_PE("s3d2c",   R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
 	DEF_GEN3_PE("s3d4c",   R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
 
-	DEF_GEN3_SD("sd0",     R8A77995_CLK_SD0,   CLK_SDSRC,     0x268),
+	DEF_GEN3_SDH("sd0h",   R8A77995_CLK_SD0H, CLK_SDSRC,         0x268),
+	DEF_GEN3_SD( "sd0",    R8A77995_CLK_SD0,  R8A77995_CLK_SD0H, 0x268),
 
 	DEF_DIV6P1("canfd",    R8A77995_CLK_CANFD, CLK_PLL0D3,    0x244),
 	DEF_DIV6P1("mso",      R8A77995_CLK_MSO,   CLK_PLL1D2,    0x014),
-- 
2.30.2


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [RFC PATCH 3/9] clk: renesas: r8a779a0: add SDnH clock to V3U
  2021-09-28 20:07 [RFC PATCH 0/9] clk/mmc: renesas_sdhi: refactor SDnH to be a seperate clock Wolfram Sang
  2021-09-28 20:07 ` [RFC PATCH 1/9] clk: renesas: gen3-cpg: add dummy SDnH clock Wolfram Sang
  2021-09-28 20:07 ` [RFC PATCH 2/9] clk: renesas: add SDnH clock to Gen3 SoCs Wolfram Sang
@ 2021-09-28 20:07 ` Wolfram Sang
  2021-10-11 18:03   ` Geert Uytterhoeven
  2021-09-28 20:07 ` [RFC PATCH 4/9] clk: renesas: gen3: switch to new SD clock handling Wolfram Sang
                   ` (5 subsequent siblings)
  8 siblings, 1 reply; 21+ messages in thread
From: Wolfram Sang @ 2021-09-28 20:07 UTC (permalink / raw)
  To: linux-renesas-soc
  Cc: linux-clk, linux-mmc, Geert Uytterhoeven, Yoshihiro Shimoda,
	Wolfram Sang

Currently a pass-through clock but we will make it a real divider clock
in the next patches.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 drivers/clk/renesas/r8a779a0-cpg-mssr.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index f16d125ca009..fb7f0cf2654a 100644
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -33,6 +33,7 @@ enum rcar_r8a779a0_clk_types {
 	CLK_TYPE_R8A779A0_PLL1,
 	CLK_TYPE_R8A779A0_PLL2X_3X,	/* PLL[23][01] */
 	CLK_TYPE_R8A779A0_PLL5,
+	CLK_TYPE_R8A779A0_SDH,
 	CLK_TYPE_R8A779A0_SD,
 	CLK_TYPE_R8A779A0_MDSEL,	/* Select parent/divider using mode pin */
 	CLK_TYPE_R8A779A0_OSC,	/* OSC EXTAL predivider and fixed divider */
@@ -84,6 +85,9 @@ enum clk_ids {
 	DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \
 		 .offset = _offset)
 
+#define DEF_SDH(_name, _id, _parent, _offset)   \
+	DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_SDH, _parent, .offset = _offset)
+
 #define DEF_SD(_name, _id, _parent, _offset)   \
 	DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_SD, _parent, .offset = _offset)
 
@@ -145,7 +149,8 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
 	DEF_FIXED("cp",		R8A779A0_CLK_CP,	CLK_EXTAL,	2, 1),
 	DEF_FIXED("cl16mck",	R8A779A0_CLK_CL16MCK,	CLK_PLL1_DIV2,	64, 1),
 
-	DEF_SD("sd0",		R8A779A0_CLK_SD0,	CLK_SDSRC,	0x870),
+	DEF_SDH("sdh0",		R8A779A0_CLK_SD0H,	CLK_SDSRC,	   0x870),
+	DEF_SD( "sd0",		R8A779A0_CLK_SD0,	R8A779A0_CLK_SD0H, 0x870),
 
 	DEF_DIV6P1("mso",	R8A779A0_CLK_MSO,	CLK_PLL5_DIV4,	0x87c),
 	DEF_DIV6P1("canfd",	R8A779A0_CLK_CANFD,	CLK_PLL5_DIV4,	0x878),
@@ -293,6 +298,10 @@ static struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,
 		div = cpg_pll_config->pll5_div;
 		break;
 
+	case CLK_TYPE_R8A779A0_SDH:
+		return cpg_sdh_clk_register(core->name, base + core->offset,
+					   __clk_get_name(parent), notifiers);
+
 	case CLK_TYPE_R8A779A0_SD:
 		return cpg_sd_clk_register(core->name, base, core->offset,
 					   __clk_get_name(parent), notifiers,
-- 
2.30.2


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [RFC PATCH 4/9] clk: renesas: gen3: switch to new SD clock handling
  2021-09-28 20:07 [RFC PATCH 0/9] clk/mmc: renesas_sdhi: refactor SDnH to be a seperate clock Wolfram Sang
                   ` (2 preceding siblings ...)
  2021-09-28 20:07 ` [RFC PATCH 3/9] clk: renesas: r8a779a0: add SDnH clock to V3U Wolfram Sang
@ 2021-09-28 20:07 ` Wolfram Sang
  2021-10-13  8:33   ` Geert Uytterhoeven
  2021-09-28 20:08 ` [RFC PATCH 5/9] clk: renesas: gen3-cpg: remove outdated SD_SKIP_FIRST Wolfram Sang
                   ` (4 subsequent siblings)
  8 siblings, 1 reply; 21+ messages in thread
From: Wolfram Sang @ 2021-09-28 20:07 UTC (permalink / raw)
  To: linux-renesas-soc
  Cc: linux-clk, linux-mmc, Geert Uytterhoeven, Yoshihiro Shimoda,
	Wolfram Sang

The old SD handling code was huge and could not handle all the details
which showed up on R-Car Gen3 SoCs meanwhile. It is time to switch to
another design. Have SDnH a seperate clock, use the existing divider
clocks and move the errata handling from the clock driver to the SDHI
driver where it belongs.

This patch removes the old SD handling code and switch to the new one.
This updates the SDHI driver at the same time. Because the SDHI driver
can only communitcate with the clock driver via clk_set_rate(), I don't
see an alternative to this flag-day-approach, so we cross subsystems
here.

The patch sadly looks messy for the CPG lib, but it is basically a huge
chunk of code removed and smaller chunks added. It looks much better
when you just view the resulting source file.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 drivers/clk/renesas/r8a779a0-cpg-mssr.c |   6 +-
 drivers/clk/renesas/rcar-cpg-lib.c      | 220 +++---------------------
 drivers/clk/renesas/rcar-cpg-lib.h      |   3 +-
 drivers/clk/renesas/rcar-gen3-cpg.c     |   5 +-
 drivers/mmc/host/renesas_sdhi.h         |   1 +
 drivers/mmc/host/renesas_sdhi_core.c    |  28 ++-
 6 files changed, 55 insertions(+), 208 deletions(-)

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index fb7f0cf2654a..6531f23a4bea 100644
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -303,10 +303,8 @@ static struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,
 					   __clk_get_name(parent), notifiers);
 
 	case CLK_TYPE_R8A779A0_SD:
-		return cpg_sd_clk_register(core->name, base, core->offset,
-					   __clk_get_name(parent), notifiers,
-					   false);
-		break;
+		return cpg_sd_clk_register(core->name, base + core->offset,
+					   __clk_get_name(parent));
 
 	case CLK_TYPE_R8A779A0_MDSEL:
 		/*
diff --git a/drivers/clk/renesas/rcar-cpg-lib.c b/drivers/clk/renesas/rcar-cpg-lib.c
index 351cb9c04f5c..043af5d9239f 100644
--- a/drivers/clk/renesas/rcar-cpg-lib.c
+++ b/drivers/clk/renesas/rcar-cpg-lib.c
@@ -66,214 +66,46 @@ void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
  * SDn Clock
  */
 
-struct clk * __init cpg_sdh_clk_register(const char *name,
-	void __iomem *sdnckcr, const char *parent_name,
-	struct raw_notifier_head *notifiers)
-{
-	/* placeholder during transition */
-	return clk_register_fixed_factor(NULL, name, parent_name, 0, 1, 1);
-}
-
-#define CPG_SD_STP_HCK		BIT(9)
-#define CPG_SD_STP_CK		BIT(8)
-
-#define CPG_SD_STP_MASK		(CPG_SD_STP_HCK | CPG_SD_STP_CK)
-#define CPG_SD_FC_MASK		(0x7 << 2 | 0x3 << 0)
-
-#define CPG_SD_DIV_TABLE_DATA(stp_hck, sd_srcfc, sd_fc, sd_div) \
-{ \
-	.val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
-	       ((sd_srcfc) << 2) | \
-	       ((sd_fc) << 0), \
-	.div = (sd_div), \
-}
+#define SDnSRCFC_SHIFT 2
+#define STPnHCK	BIT(9 - SDnSRCFC_SHIFT)
 
-struct sd_div_table {
-	u32 val;
-	unsigned int div;
-};
-
-struct sd_clock {
-	struct clk_hw hw;
-	const struct sd_div_table *div_table;
-	struct cpg_simple_notifier csn;
-	unsigned int div_num;
-	unsigned int cur_div_idx;
-};
-
-/* SDn divider
- *           sd_srcfc   sd_fc   div
- * stp_hck   (div)      (div)     = sd_srcfc x sd_fc
- *---------------------------------------------------------
- *  0         0 (1)      1 (4)      4 : SDR104 / HS200 / HS400 (8 TAP)
- *  0         1 (2)      1 (4)      8 : SDR50
- *  1         2 (4)      1 (4)     16 : HS / SDR25
- *  1         3 (8)      1 (4)     32 : NS / SDR12
- *  1         4 (16)     1 (4)     64
- *  0         0 (1)      0 (2)      2
- *  0         1 (2)      0 (2)      4 : SDR104 / HS200 / HS400 (4 TAP)
- *  1         2 (4)      0 (2)      8
- *  1         3 (8)      0 (2)     16
- *  1         4 (16)     0 (2)     32
- *
- *  NOTE: There is a quirk option to ignore the first row of the dividers
- *  table when searching for suitable settings. This is because HS400 on
- *  early ES versions of H3 and M3-W requires a specific setting to work.
- */
-static const struct sd_div_table cpg_sd_div_table[] = {
-/*	CPG_SD_DIV_TABLE_DATA(stp_hck,  sd_srcfc,   sd_fc,  sd_div) */
-	CPG_SD_DIV_TABLE_DATA(0,        0,          1,        4),
-	CPG_SD_DIV_TABLE_DATA(0,        1,          1,        8),
-	CPG_SD_DIV_TABLE_DATA(1,        2,          1,       16),
-	CPG_SD_DIV_TABLE_DATA(1,        3,          1,       32),
-	CPG_SD_DIV_TABLE_DATA(1,        4,          1,       64),
-	CPG_SD_DIV_TABLE_DATA(0,        0,          0,        2),
-	CPG_SD_DIV_TABLE_DATA(0,        1,          0,        4),
-	CPG_SD_DIV_TABLE_DATA(1,        2,          0,        8),
-	CPG_SD_DIV_TABLE_DATA(1,        3,          0,       16),
-	CPG_SD_DIV_TABLE_DATA(1,        4,          0,       32),
+static const struct clk_div_table cpg_sdh_div_table[] = {
+	{ 0, 1 }, { 1, 2 }, { STPnHCK | 2, 4 }, { STPnHCK | 3, 8 },
+	{ STPnHCK | 4, 16 }, { 0, 0 },
 };
 
-#define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)
-
-static int cpg_sd_clock_enable(struct clk_hw *hw)
-{
-	struct sd_clock *clock = to_sd_clock(hw);
-
-	cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK,
-		       clock->div_table[clock->cur_div_idx].val &
-		       CPG_SD_STP_MASK);
-
-	return 0;
-}
-
-static void cpg_sd_clock_disable(struct clk_hw *hw)
-{
-	struct sd_clock *clock = to_sd_clock(hw);
-
-	cpg_reg_modify(clock->csn.reg, 0, CPG_SD_STP_MASK);
-}
-
-static int cpg_sd_clock_is_enabled(struct clk_hw *hw)
-{
-	struct sd_clock *clock = to_sd_clock(hw);
-
-	return !(readl(clock->csn.reg) & CPG_SD_STP_MASK);
-}
-
-static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
-						unsigned long parent_rate)
-{
-	struct sd_clock *clock = to_sd_clock(hw);
-
-	return DIV_ROUND_CLOSEST(parent_rate,
-				 clock->div_table[clock->cur_div_idx].div);
-}
-
-static int cpg_sd_clock_determine_rate(struct clk_hw *hw,
-				       struct clk_rate_request *req)
-{
-	unsigned long best_rate = ULONG_MAX, diff_min = ULONG_MAX;
-	struct sd_clock *clock = to_sd_clock(hw);
-	unsigned long calc_rate, diff;
-	unsigned int i;
-
-	for (i = 0; i < clock->div_num; i++) {
-		calc_rate = DIV_ROUND_CLOSEST(req->best_parent_rate,
-					      clock->div_table[i].div);
-		if (calc_rate < req->min_rate || calc_rate > req->max_rate)
-			continue;
-
-		diff = calc_rate > req->rate ? calc_rate - req->rate
-					     : req->rate - calc_rate;
-		if (diff < diff_min) {
-			best_rate = calc_rate;
-			diff_min = diff;
-		}
-	}
-
-	if (best_rate == ULONG_MAX)
-		return -EINVAL;
-
-	req->rate = best_rate;
-	return 0;
-}
-
-static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
-				 unsigned long parent_rate)
+struct clk * __init cpg_sdh_clk_register(const char *name,
+	void __iomem *sdnckcr, const char *parent_name,
+	struct raw_notifier_head *notifiers)
 {
-	struct sd_clock *clock = to_sd_clock(hw);
-	unsigned int i;
-
-	for (i = 0; i < clock->div_num; i++)
-		if (rate == DIV_ROUND_CLOSEST(parent_rate,
-					      clock->div_table[i].div))
-			break;
+	struct cpg_simple_notifier *csn;
+	struct clk *clk;
 
-	if (i >= clock->div_num)
-		return -EINVAL;
+	csn = kzalloc(sizeof(*csn), GFP_KERNEL);
+	if (!csn)
+		return ERR_PTR(-ENOMEM);
 
-	clock->cur_div_idx = i;
+	csn->reg = sdnckcr;
 
-	cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK | CPG_SD_FC_MASK,
-		       clock->div_table[i].val &
-		       (CPG_SD_STP_MASK | CPG_SD_FC_MASK));
+	clk = clk_register_divider_table(NULL, name, parent_name, 0, sdnckcr,
+					 SDnSRCFC_SHIFT, 8, 0, cpg_sdh_div_table,
+					 &cpg_lock);
+	if (IS_ERR(clk))
+		return clk;
 
-	return 0;
+	cpg_simple_notifier_register(notifiers, csn);
+	return clk;
 }
 
-static const struct clk_ops cpg_sd_clock_ops = {
-	.enable = cpg_sd_clock_enable,
-	.disable = cpg_sd_clock_disable,
-	.is_enabled = cpg_sd_clock_is_enabled,
-	.recalc_rate = cpg_sd_clock_recalc_rate,
-	.determine_rate = cpg_sd_clock_determine_rate,
-	.set_rate = cpg_sd_clock_set_rate,
+static const struct clk_div_table cpg_sd_div_table[] = {
+	{ 0, 2 }, { 1, 4 }, { 0, 0 },
 };
 
 struct clk * __init cpg_sd_clk_register(const char *name,
-	void __iomem *base, unsigned int offset, const char *parent_name,
-	struct raw_notifier_head *notifiers, bool skip_first)
+	void __iomem *sdnckcr, const char *parent_name)
 {
-	struct clk_init_data init = {};
-	struct sd_clock *clock;
-	struct clk *clk;
-	u32 val;
-
-	clock = kzalloc(sizeof(*clock), GFP_KERNEL);
-	if (!clock)
-		return ERR_PTR(-ENOMEM);
-
-	init.name = name;
-	init.ops = &cpg_sd_clock_ops;
-	init.flags = CLK_SET_RATE_PARENT;
-	init.parent_names = &parent_name;
-	init.num_parents = 1;
-
-	clock->csn.reg = base + offset;
-	clock->hw.init = &init;
-	clock->div_table = cpg_sd_div_table;
-	clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
-
-	if (skip_first) {
-		clock->div_table++;
-		clock->div_num--;
-	}
-
-	val = readl(clock->csn.reg) & ~CPG_SD_FC_MASK;
-	val |= CPG_SD_STP_MASK | (clock->div_table[0].val & CPG_SD_FC_MASK);
-	writel(val, clock->csn.reg);
-
-	clk = clk_register(NULL, &clock->hw);
-	if (IS_ERR(clk))
-		goto free_clock;
-
-	cpg_simple_notifier_register(notifiers, &clock->csn);
-	return clk;
-
-free_clock:
-	kfree(clock);
-	return clk;
+	return clk_register_divider_table(NULL, name, parent_name, 0, sdnckcr,
+					  0, 2, 0, cpg_sd_div_table, &cpg_lock);
 }
 
 
diff --git a/drivers/clk/renesas/rcar-cpg-lib.h b/drivers/clk/renesas/rcar-cpg-lib.h
index 548cb9562f35..0941c95a3006 100644
--- a/drivers/clk/renesas/rcar-cpg-lib.h
+++ b/drivers/clk/renesas/rcar-cpg-lib.h
@@ -31,7 +31,6 @@ struct clk * __init cpg_sdh_clk_register(const char *name,
 	struct raw_notifier_head *notifiers);
 
 struct clk * __init cpg_sd_clk_register(const char *name,
-	void __iomem *base, unsigned int offset, const char *parent_name,
-	struct raw_notifier_head *notifiers, bool skip_first);
+	void __iomem *sdnckcr, const char *parent_name);
 
 #endif
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 182b189bc8f4..aa0797b98e89 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -491,9 +491,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
 					   __clk_get_name(parent), notifiers);
 
 	case CLK_TYPE_GEN3_SD:
-		return cpg_sd_clk_register(core->name, base, core->offset,
-					   __clk_get_name(parent), notifiers,
-					   cpg_quirks & SD_SKIP_FIRST);
+		return cpg_sd_clk_register(core->name, base + core->offset,
+					   __clk_get_name(parent));
 
 	case CLK_TYPE_GEN3_R:
 		if (cpg_quirks & RCKCR_CKSEL) {
diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdhi.h
index 0c45e82ff0de..5fb057833fee 100644
--- a/drivers/mmc/host/renesas_sdhi.h
+++ b/drivers/mmc/host/renesas_sdhi.h
@@ -57,6 +57,7 @@ struct tmio_mmc_dma {
 
 struct renesas_sdhi {
 	struct clk *clk;
+	struct clk *clkh;
 	struct clk *clk_cd;
 	struct tmio_mmc_data mmc_data;
 	struct tmio_mmc_dma dma_priv;
diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
index 6fc4cf3c9dce..100f86d311ea 100644
--- a/drivers/mmc/host/renesas_sdhi_core.c
+++ b/drivers/mmc/host/renesas_sdhi_core.c
@@ -127,10 +127,12 @@ static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
 }
 
 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
-					    unsigned int new_clock)
+					    unsigned int wanted_clock)
 {
 	struct renesas_sdhi *priv = host_to_priv(host);
+	struct clk *ref_clk = priv->clk;
 	unsigned int freq, diff, best_freq = 0, diff_min = ~0;
+	unsigned int new_clock, clkh_mult = 1;
 	int i;
 
 	/*
@@ -141,6 +143,16 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
 	if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc))
 		return clk_get_rate(priv->clk);
 
+	if (priv->clkh) {
+		bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
+		bool need_slow_clkh = (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
+				      (host->mmc->ios.timing == MMC_TIMING_MMC_HS400);
+		clkh_mult = use_4tap && need_slow_clkh ? 2 : 4;
+		ref_clk = priv->clkh;
+	}
+
+	new_clock = wanted_clock * clkh_mult;
+
 	/*
 	 * We want the bus clock to be as close as possible to, but no
 	 * greater than, new_clock.  As we can divide by 1 << i for
@@ -148,11 +160,10 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
 	 * possible, but no greater than, new_clock << i.
 	 */
 	for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
-		freq = clk_round_rate(priv->clk, new_clock << i);
+		freq = clk_round_rate(ref_clk, new_clock << i);
 		if (freq > (new_clock << i)) {
 			/* Too fast; look for a slightly slower option */
-			freq = clk_round_rate(priv->clk,
-					      (new_clock << i) / 4 * 3);
+			freq = clk_round_rate(ref_clk, (new_clock << i) / 4 * 3);
 			if (freq > (new_clock << i))
 				continue;
 		}
@@ -164,7 +175,10 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
 		}
 	}
 
-	clk_set_rate(priv->clk, best_freq);
+	clk_set_rate(ref_clk, best_freq);
+
+	if (ref_clk == priv->clkh)
+		clk_set_rate(priv->clk, best_freq / clkh_mult);
 
 	return clk_get_rate(priv->clk);
 }
@@ -908,6 +922,10 @@ int renesas_sdhi_probe(struct platform_device *pdev,
 		return ret;
 	}
 
+	/* Fallback for old DTs */
+	if (of_device_is_compatible(pdev->dev.of_node, "renesas,rcar-gen3-sdhi"))
+		priv->clkh = clk_get_parent(clk_get_parent(priv->clk));
+
 	/*
 	 * Some controllers provide a 2nd clock just to run the internal card
 	 * detection logic. Unfortunately, the existing driver architecture does
-- 
2.30.2


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [RFC PATCH 5/9] clk: renesas: gen3-cpg: remove outdated SD_SKIP_FIRST
  2021-09-28 20:07 [RFC PATCH 0/9] clk/mmc: renesas_sdhi: refactor SDnH to be a seperate clock Wolfram Sang
                   ` (3 preceding siblings ...)
  2021-09-28 20:07 ` [RFC PATCH 4/9] clk: renesas: gen3: switch to new SD clock handling Wolfram Sang
@ 2021-09-28 20:08 ` Wolfram Sang
  2021-10-11 18:03   ` Geert Uytterhoeven
  2021-09-28 20:08 ` [RFC PATCH 6/9] dt-bindings: mmc: renesas,sdhi: add optional SDnH clock Wolfram Sang
                   ` (3 subsequent siblings)
  8 siblings, 1 reply; 21+ messages in thread
From: Wolfram Sang @ 2021-09-28 20:08 UTC (permalink / raw)
  To: linux-renesas-soc
  Cc: linux-clk, linux-mmc, Geert Uytterhoeven, Yoshihiro Shimoda,
	Wolfram Sang

We handle it differently meanwhile.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 drivers/clk/renesas/rcar-gen3-cpg.c | 15 +++------------
 1 file changed, 3 insertions(+), 12 deletions(-)

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index aa0797b98e89..c4b36c90e159 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -397,29 +397,20 @@ static u32 cpg_quirks __initdata;
 
 #define PLL_ERRATA	BIT(0)		/* Missing PLL0/2/4 post-divider */
 #define RCKCR_CKSEL	BIT(1)		/* Manual RCLK parent selection */
-#define SD_SKIP_FIRST	BIT(2)		/* Skip first clock in SD table */
 
 
 static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
 	{
 		.soc_id = "r8a7795", .revision = "ES1.0",
-		.data = (void *)(PLL_ERRATA | RCKCR_CKSEL | SD_SKIP_FIRST),
+		.data = (void *)(PLL_ERRATA | RCKCR_CKSEL),
 	},
 	{
 		.soc_id = "r8a7795", .revision = "ES1.*",
-		.data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST),
-	},
-	{
-		.soc_id = "r8a7795", .revision = "ES2.0",
-		.data = (void *)SD_SKIP_FIRST,
+		.data = (void *)(RCKCR_CKSEL),
 	},
 	{
 		.soc_id = "r8a7796", .revision = "ES1.0",
-		.data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST),
-	},
-	{
-		.soc_id = "r8a7796", .revision = "ES1.1",
-		.data = (void *)SD_SKIP_FIRST,
+		.data = (void *)(RCKCR_CKSEL),
 	},
 	{ /* sentinel */ }
 };
-- 
2.30.2


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [RFC PATCH 6/9] dt-bindings: mmc: renesas,sdhi: add optional SDnH clock
  2021-09-28 20:07 [RFC PATCH 0/9] clk/mmc: renesas_sdhi: refactor SDnH to be a seperate clock Wolfram Sang
                   ` (4 preceding siblings ...)
  2021-09-28 20:08 ` [RFC PATCH 5/9] clk: renesas: gen3-cpg: remove outdated SD_SKIP_FIRST Wolfram Sang
@ 2021-09-28 20:08 ` Wolfram Sang
  2021-10-11 18:04   ` Geert Uytterhoeven
  2021-09-28 20:08 ` [RFC PATCH 7/9] arm64: dts: r8a77951: add SDnH clocks Wolfram Sang
                   ` (2 subsequent siblings)
  8 siblings, 1 reply; 21+ messages in thread
From: Wolfram Sang @ 2021-09-28 20:08 UTC (permalink / raw)
  To: linux-renesas-soc
  Cc: linux-clk, linux-mmc, Geert Uytterhoeven, Yoshihiro Shimoda,
	Wolfram Sang

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
index 9f1e7092cf44..762a424ca76e 100644
--- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
+++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
@@ -132,12 +132,13 @@ allOf:
       properties:
         clocks:
           minItems: 1
-          maxItems: 2
+          maxItems: 3
         clock-names:
           minItems: 1
           items:
             - const: core
             - const: cd
+            - const: clkh
 
   - if:
       properties:
-- 
2.30.2


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [RFC PATCH 7/9] arm64: dts: r8a77951: add SDnH clocks
  2021-09-28 20:07 [RFC PATCH 0/9] clk/mmc: renesas_sdhi: refactor SDnH to be a seperate clock Wolfram Sang
                   ` (5 preceding siblings ...)
  2021-09-28 20:08 ` [RFC PATCH 6/9] dt-bindings: mmc: renesas,sdhi: add optional SDnH clock Wolfram Sang
@ 2021-09-28 20:08 ` Wolfram Sang
  2021-10-11 18:04   ` Geert Uytterhoeven
  2021-09-28 20:08 ` [RFC PATCH 8/9] arm64: dts: r8a77965: " Wolfram Sang
  2021-09-28 20:08 ` [RFC PATCH 9/9] mmc: renesas_sdhi: parse DT for SDnH Wolfram Sang
  8 siblings, 1 reply; 21+ messages in thread
From: Wolfram Sang @ 2021-09-28 20:08 UTC (permalink / raw)
  To: linux-renesas-soc
  Cc: linux-clk, linux-mmc, Geert Uytterhoeven, Yoshihiro Shimoda,
	Wolfram Sang

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 arch/arm64/boot/dts/renesas/r8a77951.dtsi | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi
index 1768a3e6bb8d..391ffe6ca03e 100644
--- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi
@@ -2668,7 +2668,8 @@ sdhi0: mmc@ee100000 {
 				     "renesas,rcar-gen3-sdhi";
 			reg = <0 0xee100000 0 0x2000>;
 			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 314>;
+			clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7795_CLK_SD0H>;
+			clock-names = "core", "clkh";
 			max-frequency = <200000000>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 			resets = <&cpg 314>;
@@ -2681,7 +2682,8 @@ sdhi1: mmc@ee120000 {
 				     "renesas,rcar-gen3-sdhi";
 			reg = <0 0xee120000 0 0x2000>;
 			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 313>;
+			clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7795_CLK_SD1H>;
+			clock-names = "core", "clkh";
 			max-frequency = <200000000>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 			resets = <&cpg 313>;
@@ -2694,7 +2696,8 @@ sdhi2: mmc@ee140000 {
 				     "renesas,rcar-gen3-sdhi";
 			reg = <0 0xee140000 0 0x2000>;
 			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 312>;
+			clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7795_CLK_SD2H>;
+			clock-names = "core", "clkh";
 			max-frequency = <200000000>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 			resets = <&cpg 312>;
@@ -2707,7 +2710,8 @@ sdhi3: mmc@ee160000 {
 				     "renesas,rcar-gen3-sdhi";
 			reg = <0 0xee160000 0 0x2000>;
 			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 311>;
+			clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7795_CLK_SD3H>;
+			clock-names = "core", "clkh";
 			max-frequency = <200000000>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 			resets = <&cpg 311>;
-- 
2.30.2


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [RFC PATCH 8/9] arm64: dts: r8a77965: add SDnH clocks
  2021-09-28 20:07 [RFC PATCH 0/9] clk/mmc: renesas_sdhi: refactor SDnH to be a seperate clock Wolfram Sang
                   ` (6 preceding siblings ...)
  2021-09-28 20:08 ` [RFC PATCH 7/9] arm64: dts: r8a77951: add SDnH clocks Wolfram Sang
@ 2021-09-28 20:08 ` Wolfram Sang
  2021-10-11 18:04   ` Geert Uytterhoeven
  2021-09-28 20:08 ` [RFC PATCH 9/9] mmc: renesas_sdhi: parse DT for SDnH Wolfram Sang
  8 siblings, 1 reply; 21+ messages in thread
From: Wolfram Sang @ 2021-09-28 20:08 UTC (permalink / raw)
  To: linux-renesas-soc
  Cc: linux-clk, linux-mmc, Geert Uytterhoeven, Yoshihiro Shimoda,
	Wolfram Sang

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 08df75606430..3a357d958d4a 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -2315,7 +2315,8 @@ sdhi0: mmc@ee100000 {
 				     "renesas,rcar-gen3-sdhi";
 			reg = <0 0xee100000 0 0x2000>;
 			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 314>;
+			clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77965_CLK_SD0H>;
+			clock-names = "core", "clkh";
 			max-frequency = <200000000>;
 			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
 			resets = <&cpg 314>;
@@ -2328,7 +2329,8 @@ sdhi1: mmc@ee120000 {
 				     "renesas,rcar-gen3-sdhi";
 			reg = <0 0xee120000 0 0x2000>;
 			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 313>;
+			clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77965_CLK_SD1H>;
+			clock-names = "core", "clkh";
 			max-frequency = <200000000>;
 			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
 			resets = <&cpg 313>;
@@ -2341,7 +2343,8 @@ sdhi2: mmc@ee140000 {
 				     "renesas,rcar-gen3-sdhi";
 			reg = <0 0xee140000 0 0x2000>;
 			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 312>;
+			clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77965_CLK_SD2H>;
+			clock-names = "core", "clkh";
 			max-frequency = <200000000>;
 			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
 			resets = <&cpg 312>;
@@ -2354,7 +2357,8 @@ sdhi3: mmc@ee160000 {
 				     "renesas,rcar-gen3-sdhi";
 			reg = <0 0xee160000 0 0x2000>;
 			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 311>;
+			clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77965_CLK_SD3H>;
+			clock-names = "core", "clkh";
 			max-frequency = <200000000>;
 			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
 			resets = <&cpg 311>;
-- 
2.30.2


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [RFC PATCH 9/9] mmc: renesas_sdhi: parse DT for SDnH
  2021-09-28 20:07 [RFC PATCH 0/9] clk/mmc: renesas_sdhi: refactor SDnH to be a seperate clock Wolfram Sang
                   ` (7 preceding siblings ...)
  2021-09-28 20:08 ` [RFC PATCH 8/9] arm64: dts: r8a77965: " Wolfram Sang
@ 2021-09-28 20:08 ` Wolfram Sang
  2021-10-11 18:04   ` Geert Uytterhoeven
  8 siblings, 1 reply; 21+ messages in thread
From: Wolfram Sang @ 2021-09-28 20:08 UTC (permalink / raw)
  To: linux-renesas-soc
  Cc: linux-clk, linux-mmc, Geert Uytterhoeven, Yoshihiro Shimoda,
	Wolfram Sang

If there is a SDnH clock provided in DT, let's use it instead of relying
on the fallback.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 drivers/mmc/host/renesas_sdhi_core.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
index 100f86d311ea..41a5ee80c661 100644
--- a/drivers/mmc/host/renesas_sdhi_core.c
+++ b/drivers/mmc/host/renesas_sdhi_core.c
@@ -922,8 +922,16 @@ int renesas_sdhi_probe(struct platform_device *pdev,
 		return ret;
 	}
 
+	priv->clkh = devm_clk_get_optional(&pdev->dev, "clkh");
+	if (IS_ERR(priv->clkh)) {
+		ret = PTR_ERR(priv->clkh);
+		dev_err(&pdev->dev, "cannot get clockh: %d\n", ret);
+		return ret;
+	}
+
 	/* Fallback for old DTs */
-	if (of_device_is_compatible(pdev->dev.of_node, "renesas,rcar-gen3-sdhi"))
+	if (!priv->clkh &&
+	    of_device_is_compatible(pdev->dev.of_node, "renesas,rcar-gen3-sdhi"))
 		priv->clkh = clk_get_parent(clk_get_parent(priv->clk));
 
 	/*
-- 
2.30.2


^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [RFC PATCH 1/9] clk: renesas: gen3-cpg: add dummy SDnH clock
  2021-09-28 20:07 ` [RFC PATCH 1/9] clk: renesas: gen3-cpg: add dummy SDnH clock Wolfram Sang
@ 2021-10-11 18:03   ` Geert Uytterhoeven
  0 siblings, 0 replies; 21+ messages in thread
From: Geert Uytterhoeven @ 2021-10-11 18:03 UTC (permalink / raw)
  To: Wolfram Sang; +Cc: Linux-Renesas, linux-clk, Linux MMC List, Yoshihiro Shimoda

Hi Wolfram,

clk: renesas: rcar-gen3: ...

On Tue, Sep 28, 2021 at 10:08 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> Currently, SDnH is handled together with SDn. This caused lots of
> problems, so we want SDnH as a seperate clock. Introduce a dummy SDnH

separate  (as checkpatch told me ;-)

> type here which creates a fixed-factor clock with factor 1. That allows
> us to convert the per-SoC CPG drivers while keeping the old behaviour
> for now. A later patch then will add the proper functionality.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [RFC PATCH 2/9] clk: renesas: add SDnH clock to Gen3 SoCs
  2021-09-28 20:07 ` [RFC PATCH 2/9] clk: renesas: add SDnH clock to Gen3 SoCs Wolfram Sang
@ 2021-10-11 18:03   ` Geert Uytterhoeven
  0 siblings, 0 replies; 21+ messages in thread
From: Geert Uytterhoeven @ 2021-10-11 18:03 UTC (permalink / raw)
  To: Wolfram Sang; +Cc: Linux-Renesas, linux-clk, Linux MMC List, Yoshihiro Shimoda

Hi Wolfram,

clk: renesas: rcar-gen3: ...

On Tue, Sep 28, 2021 at 10:08 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> Currently a pass-through clock but we will make it a real divider clock
> in the next patches.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

> --- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
> @@ -97,10 +97,14 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = {
>         DEF_FIXED("s3d2",       R8A774B1_CLK_S3D2,  CLK_S3,         2, 1),
>         DEF_FIXED("s3d4",       R8A774B1_CLK_S3D4,  CLK_S3,         4, 1),
>
> -       DEF_GEN3_SD("sd0",      R8A774B1_CLK_SD0,   CLK_SDSRC,     0x074),
> -       DEF_GEN3_SD("sd1",      R8A774B1_CLK_SD1,   CLK_SDSRC,     0x078),
> -       DEF_GEN3_SD("sd2",      R8A774B1_CLK_SD2,   CLK_SDSRC,     0x268),
> -       DEF_GEN3_SD("sd3",      R8A774B1_CLK_SD3,   CLK_SDSRC,     0x26c),
> +       DEF_GEN3_SDH("sd0h",    R8A774B1_CLK_SD0H,  CLK_SDSRC,         0x074),
> +       DEF_GEN3_SD( "sd0",     R8A774B1_CLK_SD0,   R8A774B1_CLK_SD0H, 0x074),
> +       DEF_GEN3_SDH("sd1h",    R8A774B1_CLK_SD1H,  CLK_SDSRC,         0x078),
> +       DEF_GEN3_SD( "sd1",     R8A774B1_CLK_SD1,   R8A774B1_CLK_SD1H, 0x078),
> +       DEF_GEN3_SDH("sd2h",    R8A774B1_CLK_SD2H,  CLK_SDSRC,         0x268),
> +       DEF_GEN3_SD( "sd2",     R8A774B1_CLK_SD2,   R8A774B1_CLK_SD2H, 0x268),
> +       DEF_GEN3_SDH("sd3h",    R8A774B1_CLK_SD3H,  CLK_SDSRC,         0x26c),
> +       DEF_GEN3_SD( "sd3",     R8A774B1_CLK_SD3,   R8A774B1_CLK_SD3H, 0x26c),

checkpatch says (also for other source files):

    WARNING: please, no space before tabs

With the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [RFC PATCH 3/9] clk: renesas: r8a779a0: add SDnH clock to V3U
  2021-09-28 20:07 ` [RFC PATCH 3/9] clk: renesas: r8a779a0: add SDnH clock to V3U Wolfram Sang
@ 2021-10-11 18:03   ` Geert Uytterhoeven
  0 siblings, 0 replies; 21+ messages in thread
From: Geert Uytterhoeven @ 2021-10-11 18:03 UTC (permalink / raw)
  To: Wolfram Sang; +Cc: Linux-Renesas, linux-clk, Linux MMC List, Yoshihiro Shimoda

On Tue, Sep 28, 2021 at 10:08 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> Currently a pass-through clock but we will make it a real divider clock
> in the next patches.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [RFC PATCH 5/9] clk: renesas: gen3-cpg: remove outdated SD_SKIP_FIRST
  2021-09-28 20:08 ` [RFC PATCH 5/9] clk: renesas: gen3-cpg: remove outdated SD_SKIP_FIRST Wolfram Sang
@ 2021-10-11 18:03   ` Geert Uytterhoeven
  0 siblings, 0 replies; 21+ messages in thread
From: Geert Uytterhoeven @ 2021-10-11 18:03 UTC (permalink / raw)
  To: Wolfram Sang; +Cc: Linux-Renesas, linux-clk, Linux MMC List, Yoshihiro Shimoda

Hi Wolfram,

clk: renesas: rcar-gen3: ...

On Tue, Sep 28, 2021 at 10:08 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> We handle it differently meanwhile.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Perhaps this should be folded into the previous patch?

Regardless:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [RFC PATCH 6/9] dt-bindings: mmc: renesas,sdhi: add optional SDnH clock
  2021-09-28 20:08 ` [RFC PATCH 6/9] dt-bindings: mmc: renesas,sdhi: add optional SDnH clock Wolfram Sang
@ 2021-10-11 18:04   ` Geert Uytterhoeven
  0 siblings, 0 replies; 21+ messages in thread
From: Geert Uytterhoeven @ 2021-10-11 18:04 UTC (permalink / raw)
  To: Wolfram Sang; +Cc: Linux-Renesas, linux-clk, Linux MMC List, Yoshihiro Shimoda

Hi Wolfram,

On Tue, Sep 28, 2021 at 10:08 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Thanks for your patch!

> --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
> +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
> @@ -132,12 +132,13 @@ allOf:
>        properties:
>          clocks:
>            minItems: 1
> -          maxItems: 2
> +          maxItems: 3
>          clock-names:
>            minItems: 1
>            items:
>              - const: core
>              - const: cd
> +            - const: clkh

This doesn't work, as the second clock is an optional clock, even if
clkh is present.

>
>    - if:
>        properties:

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [RFC PATCH 7/9] arm64: dts: r8a77951: add SDnH clocks
  2021-09-28 20:08 ` [RFC PATCH 7/9] arm64: dts: r8a77951: add SDnH clocks Wolfram Sang
@ 2021-10-11 18:04   ` Geert Uytterhoeven
  0 siblings, 0 replies; 21+ messages in thread
From: Geert Uytterhoeven @ 2021-10-11 18:04 UTC (permalink / raw)
  To: Wolfram Sang; +Cc: Linux-Renesas, linux-clk, Linux MMC List, Yoshihiro Shimoda

Hi Wolfram,

arm64: dts: renesas: r8a77951: ...

On Tue, Sep 28, 2021 at 10:08 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

> --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi
> @@ -2668,7 +2668,8 @@ sdhi0: mmc@ee100000 {
>                                      "renesas,rcar-gen3-sdhi";
>                         reg = <0 0xee100000 0 0x2000>;
>                         interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
> -                       clocks = <&cpg CPG_MOD 314>;
> +                       clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7795_CLK_SD0H>;
> +                       clock-names = "core", "clkh";
>                         max-frequency = <200000000>;
>                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
>                         resets = <&cpg 314>;
> @@ -2681,7 +2682,8 @@ sdhi1: mmc@ee120000 {
>                                      "renesas,rcar-gen3-sdhi";
>                         reg = <0 0xee120000 0 0x2000>;
>                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
> -                       clocks = <&cpg CPG_MOD 313>;
> +                       clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7795_CLK_SD1H>;
> +                       clock-names = "core", "clkh";
>                         max-frequency = <200000000>;
>                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
>                         resets = <&cpg 313>;
> @@ -2694,7 +2696,8 @@ sdhi2: mmc@ee140000 {
>                                      "renesas,rcar-gen3-sdhi";
>                         reg = <0 0xee140000 0 0x2000>;
>                         interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
> -                       clocks = <&cpg CPG_MOD 312>;
> +                       clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7795_CLK_SD2H>;
> +                       clock-names = "core", "clkh";
>                         max-frequency = <200000000>;
>                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
>                         resets = <&cpg 312>;
> @@ -2707,7 +2710,8 @@ sdhi3: mmc@ee160000 {
>                                      "renesas,rcar-gen3-sdhi";
>                         reg = <0 0xee160000 0 0x2000>;
>                         interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
> -                       clocks = <&cpg CPG_MOD 311>;
> +                       clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7795_CLK_SD3H>;
> +                       clock-names = "core", "clkh";
>                         max-frequency = <200000000>;
>                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
>                         resets = <&cpg 311>;

LGTM, but fails dtbs_check, as expected:

    mmc@ee100000: clock-names:1: 'cd' was expected
    ...

As that is a binding issue, and not an issue with this patch:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [RFC PATCH 8/9] arm64: dts: r8a77965: add SDnH clocks
  2021-09-28 20:08 ` [RFC PATCH 8/9] arm64: dts: r8a77965: " Wolfram Sang
@ 2021-10-11 18:04   ` Geert Uytterhoeven
  0 siblings, 0 replies; 21+ messages in thread
From: Geert Uytterhoeven @ 2021-10-11 18:04 UTC (permalink / raw)
  To: Wolfram Sang; +Cc: Linux-Renesas, linux-clk, Linux MMC List, Yoshihiro Shimoda

Hi Wolfram,

arm64: dts: renesas: r8a77965: ...

On Tue, Sep 28, 2021 at 10:08 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

> --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
> @@ -2315,7 +2315,8 @@ sdhi0: mmc@ee100000 {
>                                      "renesas,rcar-gen3-sdhi";
>                         reg = <0 0xee100000 0 0x2000>;
>                         interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
> -                       clocks = <&cpg CPG_MOD 314>;
> +                       clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77965_CLK_SD0H>;
> +                       clock-names = "core", "clkh";
>                         max-frequency = <200000000>;
>                         power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
>                         resets = <&cpg 314>;
> @@ -2328,7 +2329,8 @@ sdhi1: mmc@ee120000 {
>                                      "renesas,rcar-gen3-sdhi";
>                         reg = <0 0xee120000 0 0x2000>;
>                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
> -                       clocks = <&cpg CPG_MOD 313>;
> +                       clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77965_CLK_SD1H>;
> +                       clock-names = "core", "clkh";
>                         max-frequency = <200000000>;
>                         power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
>                         resets = <&cpg 313>;
> @@ -2341,7 +2343,8 @@ sdhi2: mmc@ee140000 {
>                                      "renesas,rcar-gen3-sdhi";
>                         reg = <0 0xee140000 0 0x2000>;
>                         interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
> -                       clocks = <&cpg CPG_MOD 312>;
> +                       clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77965_CLK_SD2H>;
> +                       clock-names = "core", "clkh";
>                         max-frequency = <200000000>;
>                         power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
>                         resets = <&cpg 312>;
> @@ -2354,7 +2357,8 @@ sdhi3: mmc@ee160000 {
>                                      "renesas,rcar-gen3-sdhi";
>                         reg = <0 0xee160000 0 0x2000>;
>                         interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
> -                       clocks = <&cpg CPG_MOD 311>;
> +                       clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77965_CLK_SD3H>;
> +                       clock-names = "core", "clkh";
>                         max-frequency = <200000000>;
>                         power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
>                         resets = <&cpg 311>;

LGTM, but fails dtbs_check, as expected:

    mmc@ee100000: clock-names:1: 'cd' was expected
    ...

As that is a binding issue, and not an issue with this patch:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [RFC PATCH 9/9] mmc: renesas_sdhi: parse DT for SDnH
  2021-09-28 20:08 ` [RFC PATCH 9/9] mmc: renesas_sdhi: parse DT for SDnH Wolfram Sang
@ 2021-10-11 18:04   ` Geert Uytterhoeven
  0 siblings, 0 replies; 21+ messages in thread
From: Geert Uytterhoeven @ 2021-10-11 18:04 UTC (permalink / raw)
  To: Wolfram Sang
  Cc: Linux-Renesas, linux-clk, Linux MMC List, Geert Uytterhoeven,
	Yoshihiro Shimoda

On Tue, Sep 28, 2021 at 10:08 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> If there is a SDnH clock provided in DT, let's use it instead of relying
> on the fallback.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [RFC PATCH 4/9] clk: renesas: gen3: switch to new SD clock handling
  2021-09-28 20:07 ` [RFC PATCH 4/9] clk: renesas: gen3: switch to new SD clock handling Wolfram Sang
@ 2021-10-13  8:33   ` Geert Uytterhoeven
  2021-10-21  9:59     ` Wolfram Sang
  0 siblings, 1 reply; 21+ messages in thread
From: Geert Uytterhoeven @ 2021-10-13  8:33 UTC (permalink / raw)
  To: Wolfram Sang; +Cc: Linux-Renesas, linux-clk, Linux MMC List, Yoshihiro Shimoda

Hi Wolfram,

clk: renesas: rcar-gen3: ...

Thanks for your patch!

On Tue, Sep 28, 2021 at 10:08 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> The old SD handling code was huge and could not handle all the details
> which showed up on R-Car Gen3 SoCs meanwhile. It is time to switch to
> another design. Have SDnH a seperate clock, use the existing divider

separate  (as checkpatch told me ;-)

> clocks and move the errata handling from the clock driver to the SDHI
> driver where it belongs.
>
> This patch removes the old SD handling code and switch to the new one.
> This updates the SDHI driver at the same time. Because the SDHI driver
> can only communitcate with the clock driver via clk_set_rate(), I don't

communicate (as Gmail composer told me ;-)

> see an alternative to this flag-day-approach, so we cross subsystems
> here.
>
> The patch sadly looks messy for the CPG lib, but it is basically a huge
> chunk of code removed and smaller chunks added. It looks much better
> when you just view the resulting source file.

Indeed, the end result is pretty neat.
BTW, the diff looks much better with the --histogram option of
git diff/show.

> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

> --- a/drivers/clk/renesas/rcar-cpg-lib.c
> +++ b/drivers/clk/renesas/rcar-cpg-lib.c

> -static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
> -                                unsigned long parent_rate)
> +struct clk * __init cpg_sdh_clk_register(const char *name,
> +       void __iomem *sdnckcr, const char *parent_name,
> +       struct raw_notifier_head *notifiers)
>  {
> -       struct sd_clock *clock = to_sd_clock(hw);
> -       unsigned int i;
> -
> -       for (i = 0; i < clock->div_num; i++)
> -               if (rate == DIV_ROUND_CLOSEST(parent_rate,
> -                                             clock->div_table[i].div))
> -                       break;
> +       struct cpg_simple_notifier *csn;
> +       struct clk *clk;
>
> -       if (i >= clock->div_num)
> -               return -EINVAL;
> +       csn = kzalloc(sizeof(*csn), GFP_KERNEL);
> +       if (!csn)
> +               return ERR_PTR(-ENOMEM);
>
> -       clock->cur_div_idx = i;
> +       csn->reg = sdnckcr;
>
> -       cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK | CPG_SD_FC_MASK,
> -                      clock->div_table[i].val &
> -                      (CPG_SD_STP_MASK | CPG_SD_FC_MASK));
> +       clk = clk_register_divider_table(NULL, name, parent_name, 0, sdnckcr,
> +                                        SDnSRCFC_SHIFT, 8, 0, cpg_sdh_div_table,
> +                                        &cpg_lock);
> +       if (IS_ERR(clk))
> +               return clk;

Missing "kfree(csn)".

>
> -       return 0;
> +       cpg_simple_notifier_register(notifiers, csn);
> +       return clk;
>  }

>  struct clk * __init cpg_sd_clk_register(const char *name,
> -       void __iomem *base, unsigned int offset, const char *parent_name,
> -       struct raw_notifier_head *notifiers, bool skip_first)
> +       void __iomem *sdnckcr, const char *parent_name)
>  {
> -       struct clk_init_data init = {};
> -       struct sd_clock *clock;
> -       struct clk *clk;
> -       u32 val;
> -
> -       clock = kzalloc(sizeof(*clock), GFP_KERNEL);
> -       if (!clock)
> -               return ERR_PTR(-ENOMEM);
> -
> -       init.name = name;
> -       init.ops = &cpg_sd_clock_ops;
> -       init.flags = CLK_SET_RATE_PARENT;
> -       init.parent_names = &parent_name;
> -       init.num_parents = 1;
> -
> -       clock->csn.reg = base + offset;
> -       clock->hw.init = &init;
> -       clock->div_table = cpg_sd_div_table;
> -       clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
> -
> -       if (skip_first) {
> -               clock->div_table++;
> -               clock->div_num--;
> -       }
> -
> -       val = readl(clock->csn.reg) & ~CPG_SD_FC_MASK;
> -       val |= CPG_SD_STP_MASK | (clock->div_table[0].val & CPG_SD_FC_MASK);
> -       writel(val, clock->csn.reg);
> -
> -       clk = clk_register(NULL, &clock->hw);
> -       if (IS_ERR(clk))
> -               goto free_clock;
> -
> -       cpg_simple_notifier_register(notifiers, &clock->csn);
> -       return clk;
> -
> -free_clock:
> -       kfree(clock);
> -       return clk;
> +       return clk_register_divider_table(NULL, name, parent_name, 0, sdnckcr,
> +                                         0, 2, 0, cpg_sd_div_table, &cpg_lock);

So the SDn clock can no longer be disabled, as CPG_SD_STP_CK
handling is gone?

>  }

> --- a/drivers/mmc/host/renesas_sdhi_core.c
> +++ b/drivers/mmc/host/renesas_sdhi_core.c

> @@ -141,6 +143,16 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
>         if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc))
>                 return clk_get_rate(priv->clk);
>
> +       if (priv->clkh) {
> +               bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
> +               bool need_slow_clkh = (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
> +                                     (host->mmc->ios.timing == MMC_TIMING_MMC_HS400);
> +               clkh_mult = use_4tap && need_slow_clkh ? 2 : 4;
> +               ref_clk = priv->clkh;
> +       }
> +
> +       new_clock = wanted_clock * clkh_mult;
> +
>         /*
>          * We want the bus clock to be as close as possible to, but no
>          * greater than, new_clock.  As we can divide by 1 << i for
> @@ -148,11 +160,10 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
>          * possible, but no greater than, new_clock << i.
>          */
>         for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
> -               freq = clk_round_rate(priv->clk, new_clock << i);
> +               freq = clk_round_rate(ref_clk, new_clock << i);
>                 if (freq > (new_clock << i)) {
>                         /* Too fast; look for a slightly slower option */
> -                       freq = clk_round_rate(priv->clk,
> -                                             (new_clock << i) / 4 * 3);
> +                       freq = clk_round_rate(ref_clk, (new_clock << i) / 4 * 3);
>                         if (freq > (new_clock << i))
>                                 continue;
>                 }
> @@ -164,7 +175,10 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
>                 }
>         }
>
> -       clk_set_rate(priv->clk, best_freq);
> +       clk_set_rate(ref_clk, best_freq);
> +
> +       if (ref_clk == priv->clkh)

"if (priv->clkh)", for consistency with above?

> +               clk_set_rate(priv->clk, best_freq / clkh_mult);
>
>         return clk_get_rate(priv->clk);
>  }
> @@ -908,6 +922,10 @@ int renesas_sdhi_probe(struct platform_device *pdev,
>                 return ret;
>         }
>
> +       /* Fallback for old DTs */
> +       if (of_device_is_compatible(pdev->dev.of_node, "renesas,rcar-gen3-sdhi"))

I think it would be cleaner to check a flag in struct
renesas_sdhi_of_data instead.

> +               priv->clkh = clk_get_parent(clk_get_parent(priv->clk));
> +
>         /*
>          * Some controllers provide a 2nd clock just to run the internal card
>          * detection logic. Unfortunately, the existing driver architecture does

The core looks good to me, but I have to admit I'm no expert on the
SDHn/SDn clock relations and the various SDHI transfer modes.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [RFC PATCH 4/9] clk: renesas: gen3: switch to new SD clock handling
  2021-10-13  8:33   ` Geert Uytterhoeven
@ 2021-10-21  9:59     ` Wolfram Sang
  2021-10-21 11:10       ` Geert Uytterhoeven
  0 siblings, 1 reply; 21+ messages in thread
From: Wolfram Sang @ 2021-10-21  9:59 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Linux-Renesas, linux-clk, Linux MMC List, Yoshihiro Shimoda

[-- Attachment #1: Type: text/plain, Size: 2023 bytes --]

Hi Geert,

> BTW, the diff looks much better with the --histogram option of
> git diff/show.

Thanks, I tend to forget this option.

> > +       if (IS_ERR(clk))
> > +               return clk;
> 
> Missing "kfree(csn)".

Ouch, yes!

> > +       return clk_register_divider_table(NULL, name, parent_name, 0, sdnckcr,
> > +                                         0, 2, 0, cpg_sd_div_table, &cpg_lock);
> 
> So the SDn clock can no longer be disabled, as CPG_SD_STP_CK
> handling is gone?

Yes. I thought we can do it since we had 7f2c2f38c1c0 ("clk: renesas:
rcar-gen3: Remove stp_ck handling for SDHI") anyhow.

> > +       if (ref_clk == priv->clkh)
> 
> "if (priv->clkh)", for consistency with above?

Can do. I even had this originally. Then, I thought the comparison makes
it easier to understand. But it seems, it is understandable enough
without the comparison.

> > +       /* Fallback for old DTs */
> > +       if (of_device_is_compatible(pdev->dev.of_node, "renesas,rcar-gen3-sdhi"))
> 
> I think it would be cleaner to check a flag in struct
> renesas_sdhi_of_data instead.

Because new SoCs with the fallback compatible might show up?

> >          * Some controllers provide a 2nd clock just to run the internal card
> >          * detection logic. Unfortunately, the existing driver architecture does
> 
> The core looks good to me, but I have to admit I'm no expert on the
> SDHn/SDn clock relations and the various SDHI transfer modes.

I am really glad you like the changes in general. And you point to the
reason for this change. All the clock relations of the SDHI transfer
modes should go into the SDHI driver. Now, we can control SDnH and SDn
seperately, so the SDHI driver can do the proper things depending on the
mode and the quirks of the SDHI instance. I really think the clock
driver part should be as simple as it is with this series.

Thanks for the review, I will fix the other minor issues soon as well.

Happy hacking,

   Wolfram


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^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [RFC PATCH 4/9] clk: renesas: gen3: switch to new SD clock handling
  2021-10-21  9:59     ` Wolfram Sang
@ 2021-10-21 11:10       ` Geert Uytterhoeven
  0 siblings, 0 replies; 21+ messages in thread
From: Geert Uytterhoeven @ 2021-10-21 11:10 UTC (permalink / raw)
  To: Wolfram Sang, Linux-Renesas, linux-clk, Linux MMC List,
	Yoshihiro Shimoda

Hi Wolfram,

On Thu, Oct 21, 2021 at 11:59 AM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> > > +       return clk_register_divider_table(NULL, name, parent_name, 0, sdnckcr,
> > > +                                         0, 2, 0, cpg_sd_div_table, &cpg_lock);
> >
> > So the SDn clock can no longer be disabled, as CPG_SD_STP_CK
> > handling is gone?
>
> Yes. I thought we can do it since we had 7f2c2f38c1c0 ("clk: renesas:
> rcar-gen3: Remove stp_ck handling for SDHI") anyhow.

OK.

> > > +       /* Fallback for old DTs */
> > > +       if (of_device_is_compatible(pdev->dev.of_node, "renesas,rcar-gen3-sdhi"))
> >
> > I think it would be cleaner to check a flag in struct
> > renesas_sdhi_of_data instead.
>
> Because new SoCs with the fallback compatible might show up?

Because it's frowned upon to sprinkle of_device_is_compatible()
calls all over the code, especially if you already use
of_device_get_match_data().

> > >          * Some controllers provide a 2nd clock just to run the internal card
> > >          * detection logic. Unfortunately, the existing driver architecture does
> >
> > The core looks good to me, but I have to admit I'm no expert on the
> > SDHn/SDn clock relations and the various SDHI transfer modes.
>
> I am really glad you like the changes in general. And you point to the
> reason for this change. All the clock relations of the SDHI transfer
> modes should go into the SDHI driver. Now, we can control SDnH and SDn
> seperately, so the SDHI driver can do the proper things depending on the
> mode and the quirks of the SDHI instance. I really think the clock
> driver part should be as simple as it is with this series.

Good!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 21+ messages in thread

end of thread, other threads:[~2021-10-21 11:10 UTC | newest]

Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-09-28 20:07 [RFC PATCH 0/9] clk/mmc: renesas_sdhi: refactor SDnH to be a seperate clock Wolfram Sang
2021-09-28 20:07 ` [RFC PATCH 1/9] clk: renesas: gen3-cpg: add dummy SDnH clock Wolfram Sang
2021-10-11 18:03   ` Geert Uytterhoeven
2021-09-28 20:07 ` [RFC PATCH 2/9] clk: renesas: add SDnH clock to Gen3 SoCs Wolfram Sang
2021-10-11 18:03   ` Geert Uytterhoeven
2021-09-28 20:07 ` [RFC PATCH 3/9] clk: renesas: r8a779a0: add SDnH clock to V3U Wolfram Sang
2021-10-11 18:03   ` Geert Uytterhoeven
2021-09-28 20:07 ` [RFC PATCH 4/9] clk: renesas: gen3: switch to new SD clock handling Wolfram Sang
2021-10-13  8:33   ` Geert Uytterhoeven
2021-10-21  9:59     ` Wolfram Sang
2021-10-21 11:10       ` Geert Uytterhoeven
2021-09-28 20:08 ` [RFC PATCH 5/9] clk: renesas: gen3-cpg: remove outdated SD_SKIP_FIRST Wolfram Sang
2021-10-11 18:03   ` Geert Uytterhoeven
2021-09-28 20:08 ` [RFC PATCH 6/9] dt-bindings: mmc: renesas,sdhi: add optional SDnH clock Wolfram Sang
2021-10-11 18:04   ` Geert Uytterhoeven
2021-09-28 20:08 ` [RFC PATCH 7/9] arm64: dts: r8a77951: add SDnH clocks Wolfram Sang
2021-10-11 18:04   ` Geert Uytterhoeven
2021-09-28 20:08 ` [RFC PATCH 8/9] arm64: dts: r8a77965: " Wolfram Sang
2021-10-11 18:04   ` Geert Uytterhoeven
2021-09-28 20:08 ` [RFC PATCH 9/9] mmc: renesas_sdhi: parse DT for SDnH Wolfram Sang
2021-10-11 18:04   ` Geert Uytterhoeven

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