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From: Ben Widawsky <ben.widawsky@intel.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: linux-cxl@vger.kernel.org,
	Chet Douglas <chet.r.douglas@intel.com>,
	Alison Schofield <alison.schofield@intel.com>,
	Dan Williams <dan.j.williams@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>
Subject: Re: [RFC PATCH v2 13/28] cxl: Flesh out register names
Date: Wed, 3 Nov 2021 10:05:52 -0700	[thread overview]
Message-ID: <20211103170552.55ae5u7uvurkync6@intel.com> (raw)
In-Reply-To: <20211103164232.00004aff@Huawei.com>

On 21-11-03 16:42:32, Jonathan Cameron wrote:
> On Wed, 3 Nov 2021 09:03:36 -0700
> Ben Widawsky <ben.widawsky@intel.com> wrote:
> 
> > On 21-11-03 15:53:59, Jonathan Cameron wrote:
> > > On Fri, 22 Oct 2021 11:36:54 -0700
> > > Ben Widawsky <ben.widawsky@intel.com> wrote:
> > >   
> > 
> > [snip]
> > 
> > > > diff --git a/drivers/cxl/pci.h b/drivers/cxl/pci.h
> > > > index 12fdcb1b14e5..fe2898b17736 100644
> > > > --- a/drivers/cxl/pci.h
> > > > +++ b/drivers/cxl/pci.h
> > > > @@ -7,17 +7,36 @@
> > > >  
> > > >  /*
> > > >   * See section 8.1 Configuration Space Registers in the CXL 2.0
> > > > - * Specification
> > > > + * Specification. Names are taken straight from the specification with "CXL" and
> > > > + * "DVSEC" redundancies removed.
> > > >   */
> > > >  #define PCI_DVSEC_HEADER1_LENGTH_MASK	GENMASK(31, 20)
> > > >  #define PCI_DVSEC_VENDOR_ID_CXL		0x1E98
> > > > -#define PCI_DVSEC_ID_CXL		0x0
> > > >  
> > > > -#define PCI_DVSEC_ID_CXL_REGLOC_DVSEC_ID	0x8
> > > > -#define PCI_DVSEC_ID_CXL_REGLOC_BLOCK1_OFFSET	0xC
> > > > +/* 8.1.3: PCIe DVSEC for CXL Device */
> > > > +#define CXL_DVSEC_PCIE_DEVICE					0
> > > >  
> > > > -/* BAR Indicator Register (BIR) */
> > > > -#define CXL_REGLOC_BIR_MASK GENMASK(2, 0)
> > > > +/* 8.1.4: Non-CXL Function Map DVSEC */
> > > > +#define CXL_DVSEC_FUNCTION_MAP					2
> > > > +
> > > > +/* 8.1.5: CXL 2.0 Extensions DVSEC for Ports */
> > > > +#define CXL_DVSEC_PORT_EXTENSIONS				3
> > > > +
> > > > +/* 8.1.6: GPF DVSEC for CXL Port */
> > > > +#define CXL_DVSEC_PORT_GPF					4
> > > > +
> > > > +/* 8.1.7: GPF DVSEC for CXL Device */
> > > > +#define CXL_DVSEC_DEVICE_GPF					5
> > > > +
> > > > +/* 8.1.8: PCIe DVSEC for Flex Bus Port */
> > > > +#define CXL_DVSEC_PCIE_FLEXBUS_PORT				7
> > > > +
> > > > +/* 8.1.9: Register Locator DVSEC */
> > > > +#define CXL_DVSEC_REGISTER_LOCATOR				8
> > > > +#define   DVSEC_REGISTER_LOCATOR_BLOCK1_OFFSET			0xC  
> > > 
> > > Hmm. I'm not particularly keen on not having CXL in the naming for the offset
> > > and fields.  They get used in places where, to the casual reader, they may look
> > > like generic PCI_DVSEC_ defintiions....  the do get very long though, but I'm not
> > > sure that's the right place to abbreviate. 
> > > 
> > > Agreed with your comment in the thread that it's really hard to
> > > get a good consistent model for what are near enough free form names
> > > in a spec (or seem like it when read long after they were defined).
> > >   
> > 
> > Hi Jonathan, thanks for looking.
> > 
> > Well for these in particular, I'd expect the actual register/DVSEC offset to
> > have been read a few lines above, so I'm not too worried about these ones
> > specifically. However, it's a good point as this grows it may become
> > problematic. Do you have a suggestion? My ideal would be for the CXL consortium
> > to publish header files for these things and then we can just grumble about how
> > silly they are and move along, but I'm not sure that will happen.
> 
> :)  You can propose it... - Can you imagine how long those calls would go on
> for??????
> 
> > 
> > Anyway... I really don't care what we choose as long as it's consistent. What
> > color would you like?
> 
> Blue, no yellow.... Ahhhhhhh!
> 
> I think a bit of flexibility on abbreviations is needed when they get insanely
> long...  Meh, we can always rename them all later when we decide the choice was
> wrong.

Two very good choices. Ack. I'll respin. Let me spell out though in case it
wasn't clear, my goal was to make something grepable, which abbreviations take
away from. This is because as the 3.0 spec goes through I'm noticing our chapter
references are no longer 100% accurate (annoying!).

> 
> > 
> > [snip]
> > 
> 

  reply	other threads:[~2021-11-03 17:15 UTC|newest]

Thread overview: 112+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-22 18:36 [RFC PATCH v2 00/28] CXL Region Creation / HDM decoder programming Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 01/28] cxl: Rename CXL_MEM to CXL_PCI Ben Widawsky
2021-10-29 20:15   ` Dan Williams
2021-10-29 21:20     ` Ben Widawsky
2021-10-29 21:39       ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 02/28] cxl: Move register block enumeration to core Ben Widawsky
2021-10-29 20:23   ` Dan Williams
2021-10-29 21:23     ` Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 03/28] cxl/acpi: Map component registers for Root Ports Ben Widawsky
2021-10-29 20:28   ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 04/28] cxl: Add helper for new drivers Ben Widawsky
2021-10-29 20:30   ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 05/28] cxl/core: Convert decoder range to resource Ben Widawsky
2021-10-29 20:50   ` Dan Williams
2021-10-29 21:26     ` Ben Widawsky
2021-10-29 22:22       ` Dan Williams
2021-10-29 22:37         ` Ben Widawsky
2021-11-01 14:33           ` Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 06/28] cxl: Introduce endpoint decoders Ben Widawsky
2021-10-29 21:00   ` Dan Williams
2021-10-29 22:02     ` Ben Widawsky
2021-10-29 22:25       ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 07/28] cxl/core: Move target population locking to caller Ben Widawsky
2021-10-29 23:03   ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 08/28] cxl/port: Introduce a port driver Ben Widawsky
2021-10-30  1:37   ` Dan Williams
2021-10-31 17:53     ` Dan Williams
2021-10-31 18:10       ` Dan Williams
2021-11-01 17:36         ` Ben Widawsky
2021-11-01 17:53     ` Ben Widawsky
2021-11-01 17:54       ` Ben Widawsky
2021-11-02  3:31       ` Dan Williams
2021-11-02 16:27         ` Ben Widawsky
2021-11-02 17:21           ` Dan Williams
2021-11-02 16:58         ` Ben Widawsky
2021-11-04 19:10           ` Dan Williams
2021-11-04 19:49             ` Ben Widawsky
2021-11-04 20:04               ` Dan Williams
2021-11-04 21:25                 ` Ben Widawsky
2021-11-04 16:37     ` Ben Widawsky
2021-11-04 19:17       ` Dan Williams
2021-11-04 19:46         ` Ben Widawsky
2021-11-04 20:00           ` Dan Williams
2021-11-04 21:26             ` Ben Widawsky
2021-11-03 15:18   ` Jonathan Cameron
2021-10-22 18:36 ` [RFC PATCH v2 09/28] cxl/acpi: Map single port host bridge component registers Ben Widawsky
2021-10-31 18:03   ` Dan Williams
2021-11-01 17:07     ` Ben Widawsky
2021-11-02  2:15       ` Dan Williams
2021-11-02 16:31         ` Ben Widawsky
2021-11-02 17:46           ` Dan Williams
2021-11-02 17:57             ` Ben Widawsky
2021-11-02 18:10               ` Dan Williams
2021-11-02 18:27                 ` Ben Widawsky
2021-11-02 18:49                   ` Dan Williams
2021-11-02 21:15                     ` Ben Widawsky
2021-11-02 21:34                       ` Dan Williams
2021-11-02 21:47                         ` Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 10/28] cxl/core: Store global list of root ports Ben Widawsky
2021-10-31 18:32   ` Dan Williams
2021-11-01 18:43     ` Ben Widawsky
2021-11-02  2:04       ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 11/28] cxl/acpi: Rescan bus at probe completion Ben Widawsky
2021-10-31 19:25   ` Dan Williams
2021-11-01 18:56     ` Ben Widawsky
2021-11-01 21:45       ` Ben Widawsky
2021-11-02  1:56         ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 12/28] cxl/core: Store component register base for memdevs Ben Widawsky
2021-10-31 20:13   ` Dan Williams
2021-11-01 21:50     ` Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 13/28] cxl: Flesh out register names Ben Widawsky
2021-10-31 20:18   ` Dan Williams
2021-11-01 22:00     ` Ben Widawsky
2021-11-02  1:53       ` Dan Williams
2021-11-03 15:53   ` Jonathan Cameron
2021-11-03 16:03     ` Ben Widawsky
2021-11-03 16:42       ` Jonathan Cameron
2021-11-03 17:05         ` Ben Widawsky [this message]
2021-10-22 18:36 ` [RFC PATCH v2 14/28] cxl: Hide devm host for ports Ben Widawsky
2021-10-31 21:14   ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 15/28] cxl/core: Introduce API to scan switch ports Ben Widawsky
2021-11-01  5:39   ` Dan Williams
2021-11-01 22:56     ` Ben Widawsky
2021-11-02  1:45       ` Dan Williams
2021-11-02 16:39         ` Ben Widawsky
2021-11-02 20:00           ` Dan Williams
2021-11-16 16:50         ` Ben Widawsky
2021-11-16 17:51           ` Dan Williams
2021-11-16 18:02             ` Ben Widawsky
2021-11-03 16:08   ` Jonathan Cameron
2021-11-10 17:49     ` Ben Widawsky
2021-11-10 18:10       ` Jonathan Cameron
2021-11-10 21:03         ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 16/28] cxl: Introduce cxl_mem driver Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 17/28] cxl: Disable switch hierarchies for now Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 18/28] cxl/region: Add region creation ABI Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 19/28] cxl/region: Introduce concept of region configuration Ben Widawsky
2021-12-15 17:47   ` Jonathan Cameron
2021-10-22 18:37 ` [RFC PATCH v2 20/28] cxl/region: Introduce a cxl_region driver Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 21/28] cxl/acpi: Handle address space allocation Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 22/28] cxl/region: Address " Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 23/28] cxl/region: Implement XHB verification Ben Widawsky
2022-01-06 16:55   ` Jonathan Cameron
2022-01-06 16:58     ` Ben Widawsky
2022-01-06 17:33       ` Jonathan Cameron
2022-01-06 18:10         ` Jonathan Cameron
2022-01-06 18:34           ` Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 24/28] cxl/region: HB port config verification Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 25/28] cxl/region: Record host bridge target list Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 26/28] cxl/mem: Store the endpoint's uport Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 27/28] cxl/region: Gather HDM decoder resources Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 28/28] cxl: Program decoders for regions Ben Widawsky

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